376 datasheet(9/95 Pages) INTEL

9 / 95 page

376 EMBEDDED PROCESSOR

Table 21 Flag Definitions

Bit Position

Name

Function

0CF

Carry Flag

Set on high-order bit carry or borrow cleared otherwise

2PF

Parity Flag

Set if low-order 8 bits of result contain an even number

of 1-bits cleared otherwise

4AF

Auxiliary Carry Flag

Set on carry from or borrow to the low order

four bits of AL cleared otherwise

6ZF

Zero Flag

Set if result is zero cleared otherwise

7SF

Sign Flag

Set equal to high-order bit of result (0 if positive 1 if

negative)

8TF

Single Step Flag

Once set a single step interrupt occurs after the

next instruction executes TF is cleared by the single step interrupt

9IF

Interrupt-Enable Flag

When set external interrupts signaled on the

INTR pin will cause the CPU to transfer control to an interrupt vector

specified location

Direction Flag

Causes string instructions to auto-increment (default)

the appropriate index registers when cleared Setting DF causes auto-

decrement

Overflow Flag

Set if the operation resulted in a carryborrow into

the sign bit (high-order bit) of the result but did not result in a

carryborrow out of the high-order bit or vice-versa

12 13

IOPL

IO Privilege Level

Indicates the maximum CPL permitted to

execute IO instructions without generating an exception 13 fault or

consulting the IO permission bit map It also indicates the maximum

CPL value allowing alteration of the IF bit

Nested Task

Indicates that the execution of the current task is

nested within another task (see Task Switching)

Resume Flag

Used in conjunction with debug register breakpoints It

is checked at instruction boundaries before breakpoint processing If

set any debug fault is ignored on the next instruction It is reset at the

successful completion of any instruction except IRET POPF and

those instructions causing task switches

CONTROL REGISTER

The 80376 has a 32-bit control register called CR0 that is used to control coprocessor emulation This register

is shown in Figures 21 and 22 The defined CR0 bits are described in Table 22 Bits 0 4 and 31 of CR0 have

fixed values in the 80376 These values cannot be changed Programs that load CR0 should always load bits

0 4 and 31 with values previously there to be compatible with the 80386

Table 22 CR0 Definitions

Bit Position

Name

Function

1MP

Monitor Coprocessor Extension

Allows WAIT instructions to cause

a processor extension not present exception (number 7)

2EM

Emulate Processor Extension

When set

this bit causes a

processor extension not present exception (number 7) on ESC

instructions to allow processor extension emulation

3TS

Task Switched

When set this bit indicates the next instruction using

a processor extension will cause exception 7 allowing software to test

whether the current processor extension context belongs to the

current task (see Task Switching)

376 Datasheet(PDF) 9 Page - Intel Corporation

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