376 datasheet(6/95 Pages) INTEL

6 / 95 page

376 EMBEDDED PROCESSOR

Symbol

Type

Name and Function

HLDA

BUS HOLD ACKNOWLEDGE

output indicates that the 80376 has

surrendered control of its local bus to another bus master See Bus

Arbitration Signals

in Section 41 for additional information

INTR

INTERRUPT REQUEST

is a maskable input that signals the 80376 to

suspend execution of the current program and execute an interrupt

acknowledge function See Interrupt Signals in Section 41 for

additional information

NMI

NON-MASKABLE INTERRUPT REQUEST

is a non-maskable input

that signals the 80376 to suspend execution of the current program

and execute an interrupt acknowledge function See Interrupt Signals

in Section 41 for additional information

BUSY

signals a busy condition from a processor extension See

Coprocessor Interface Signals

in Section 41 for additional

information

ERROR

signals an error condition from a processor extension See

Coprocessor Interface Signals

in Section 41 for additional

information

PEREQ

PROCESSOR EXTENSION REQUEST

indicates that the processor

extension has data to be transferred by the 80376 See Coprocessor

Interface Signals

in Section 41 for additional information

FLT

FLOAT

when active forces all bidirectional and output signals

including HLDA to the float condition FLOAT is not available on the

PGA package See Float for additional information

NO CONNECT

should always remain unconnected Connection of a

NC pin may cause the processor to malfunction or be incompatible

with future steppings of the 80376

VCC

SYSTEM POWER

provides the a5V nominal DC supply input

VSS

SYSTEM GROUND

provides 0V connection from which all inputs and

outputs are measured

20 ARCHITECTURE OVERVIEW

The 80376 supports the protection mechanisms

needed by sophisticated multitasking embedded

systems and real-time operating systems The use

of these protection mechanisms is completely op-

tional For embedded applications not needing pro-

tection the 80376 can easily be configured to pro-

vide a 16 Mbyte physical address space

Instruction pipelining high bus bandwidth and a

very high performance ALU ensure short average

instruction

execution

times

and

high

system

throughput The 80376 is capable of execution at

sustained rates of 25 – 30 million instructions per

second

The 80376 offers on-chip testability and debugging

features Four break point registers allow conditional

or unconditional break point traps on code execution

or data accesses for powerful debugging of even

ROM based systems Other testability features in-

clude self-test and tri-stating of output buffers during

RESET

The Intel 80376 embedded processor consists of a

central processing unit a memory management unit

and a bus interface The central processing unit con-

sists of the execution unit and instruction unit The

execution unit contains the eight 32-bit general reg-

isters which are used for both address calculation

and data operations and a 64-bit barrel shifter used

to speed shift rotate multiply and divide operations

The instruction unit decodes the instruction opcodes

and stores them in the decoded instruction queue

for immediate use by the execution unit

The Memory Management Unit (MMU) consists of a

segmentation and protection unit Segmentation al-

lows the managing of the logical address space by

providing an extra addressing component one that

allows easy code and data relocatability and effi-

cient sharing

The protection unit provides four levels of protection

for isolating and protecting applications and the op-

erating system from each other The hardware en-

forced protection allows the design of systems with

a high degree of integrity and simplifies debugging

Finally to facilitate high performance system hard-

ware designs the 80376 bus interface offers ad-

dress pipelining and direct Byte Enable signals for

each byte of the data bus

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