376 datasheet(32/95 Pages) INTEL

32 / 95 page

376 EMBEDDED PROCESSOR

PROTECTION AND IO PERMISSION BIT MAP

The IO instructions that directly refer to addresses

in the processor’s IO space are IN INS OUT and

OUTS The 80376 has the ability to selectively trap

references to specific IO addresses The structure

that enables selective trapping is the IO Permis-

sion Bit Map in the TSS segment (see Figures 37

and 38) The IO permission map is a bit vector

The size of the map and its location in the TSS seg-

ment are variable The processor locates the IO

permission map by means of the IO map base field

in the fixed portion of the TSS The IO map base

field is 16 bits wide and contains the offset of the

beginning of the IO permission map

If an IO instruction (IN INS OUT or OUTS) is en-

countered

the processor first checks whether

CPL s IOPL If this condition is true the IO opera-

tion may proceed If not true the processor checks

the IO permission map

Each bit in the map corresponds to an IO port byte

address for example the bit for port 41 is found at

IO map base a

5 linearly (5 c 8 e 40) bit offset

1 The processor tests all the bits that correspond to

the IO addresses spanned by an IO operation for

example a double word operation tests four bits cor-

responding to four adjacent byte addresses If any

tested bit is set the processor signals a general pro-

tection exception If all the tested bits are zero the

IO operations may proceed

It is not necessary for the IO permission map to

represent all the IO addresses IO addresses not

spanned by the map are treated as if they had one-

bits in the map The IO map base should be at

least one byte less than the TSS limit and the last

byte beyond the IO mapping information must con-

tain all 1’s

Because the IO permission map is in the TSS seg-

ment different tasks can have different maps Thus

the operating system can allocate ports to a task by

changing the IO permission map in the task’s TSS

IMPORTANT IMPLEMENTATION NOTE

Beyond the last byte of IO mapping information in

the IO permission bit map must be a byte contain-

ing all 1’s The byte of all 1’s must be within the

limit of the 80376’s TSS segment (see Figure 37)

40 FUNCTIONAL DATA

The Intel 80376 embedded processor features a

straightforward functional interface to the external

hardware The 80376 has separate parallel buses

for data and address The data bus is 16 bits in

width and bidirectional The address bus outputs

24-bit address values using 23 address lines and

two-byte enable signals

The 80376 has two selectable address bus cycles

pipelined and non-pipelined The pipelining option

allows as much time as possible for data access by

240182 – 16

Figure 41 Functional Signal Groups

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