376 datasheet(93/95 Pages) INTEL

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376 EMBEDDED PROCESSOR

ENCODING OF OPERATION

DIRECTION (d) FIELD

In many two-operand instructions the d field is pres-

ent to indicate which operand is considered the

source and which is the destination

Direction of Operation

RegisterMemory k- - Register

‘‘reg’’ Field Indicates Source Operand

‘‘mod rm’’ or ‘‘mod ss index base’’ Indicates

Destination Operand

‘‘reg’’ Field Indicates Destination Operand

‘‘mod rm’’ or ‘‘mod ss index base’’ Indicates

Source Operand

ENCODING OF SIGN-EXTEND (s) FIELD

The s field occurs primarily to instructions with im-

mediate data fields The s field has an effect only if

the size of the immediate data is 8 bits and is being

placed in a 16-bit or 32-bit destination

Effect on

Immediate Data8

Immediate Data 16

l32

0 None

None

1 Sign-Extend Data8 to Fill

None

16-Bit or 32-Bit Destination

ENCODING OF CONDITIONAL

TEST (tttn) FIELD

For the conditional instructions (conditional jumps

and set on condition) tttn is encoded with n indicat-

ing to use the condition (ne0) or its negation (ne1)

and ttt giving the condition to test

Mnemonic

Condition

tttn

Overflow

0000

No Overflow

0001

BNAE

BelowNot Above or Equal

0010

NBAE

Not BelowAbove or Equal

0011

EqualZero

0100

NENZ

Not EqualNot Zero

0101

BENA

Below or EqualNot Above

0110

NBEA

Not Below or EqualAbove

0111

Sign

1000

Not Sign

1001

PPE

ParityParity Even

1010

NPPO

Not ParityParity Odd

1011

LNGE

Less ThanNot Greater or Equal

1100

NLGE

Not Less ThanGreater or Equal

1101

LENG

Less Than or EqualGreater Than 1110

NLEG

Not Less or EqualGreater Than

1111

ENCODING OF CONTROL OR DEBUG

For the loading and storing of the Control and Debug

registers

When Interpreted as Control Register Field

eee Code

Reg Name

000

CR0

010

Reserved

011

Reserved

Do not use any other encoding

When Interpreted as Debug Register Field

eee Code

Reg Name

000

DR0

001

DR1

010

DR2

011

DR3

110

DR6

111

DR7

Do not use any other encoding

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