376 datasheet(94/95 Pages) INTEL

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376 EMBEDDED PROCESSOR

90 REVISION HISTORY

The sections significantly revised since version -003 are

Section 10

Added FLT pin

Section 44

Added description of FLOAT operation and ONCE Mode Figure 420 is new

Section 46

Added revision identifier information for change to CHMOS IV manufacturing process

Section 50

Both packages now specified for 0 C – 115 C case temperature operation Thermal resist-

ance values changed

Section 63

ICC Max specifications changed from 400 mA (cold) and 360 mA (hot) to 275 mA (cold 16

MHz) and 305 mA (cold 20 MHz)

Section 64

HLDA Valid Delay t14 min changed from 6 ns to 4 ns Added 20 MHz AC specifications in

Table 65 Replaced Capacitive Derating Curves in Figures 68 – 610 to reflect new manufac-

turing process Replaced ICC vs Frequency data (Figure 611) to reflect new specifications

The sections significantly revised since version -002 are

Section 10

Modified table 11 to list pins in alphabetical order

The sections significantly revised since version -001 are

Section 20

Figure 20 was updated to show the 16-bit registers SI DI BP and SP

Section 21

Figure 22 was updated to show the correct bit polarity for bit 4 in the CR0 register

Section 21

Tables 21 and 22 were updated to include additional information on the EFLAGs and CR0

registers

Section 23

Figure 23 was updated to more accurately reflect the addressing mechanism of the 80376

Section 26

In the subsection Maskable Interrupt a paragraph was added to describe the effect of

interrupt gates on the IF EFLAGs bit

Section 28

Table 27 was updated to reflect the correct power up condition of the CR0 register

Section 210

Figure 26 was updated to show the correct bit positions of the BT BS and BD bits in the

DR6 register

Section 30

Figure 31 was updated to clearly show the address calculation process

Section 32

The subsection DESCRIPTORS was elaborated upon to clearly define the relationship be-

tween the linear address space and physical address space of the 80376

Section 32

Figures 33 and 34 were updated to show the AVL bit field

Section 33

The last sentence in the first paragraph of subsection PROTECTION AND IO PERMIS-

SION BIT MAP

was deleted This was an incorrect statement

Section 41

In the Subsection ADDRESS BUS (BHE BLE A23–A1 last sentence in the first paragraph

was updated to reflect the numerics operand addresses as 8000FCH and 8000FEH Be-

cause the 80376 sometimes does a double word IO access a second access to 8000FEH

can be seen

Section 41

The Subsection Hold Lantencies was updated to describe how 32-bit and unaligned ac-

cesses are internally locked but do not assert the LOCK signal

Section 42

Table 46 was updated to show the correct active data bits during a BLE assertion

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