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376 Datasheet(PDF) 56 Page - Intel Corporation |
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376 Datasheet(HTML) 56 Page - Intel Corporation |
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56 / 95 page  376 EMBEDDED PROCESSOR 240182 – 33 NOTE HOLD is a synchronous input and can be asserted at any CLK2 edge provided setup and hold (t23 and t24) require- ments are met This waveform is useful for determining Hold Acknowledge latency Figure 418 Requesting Hold from Idle Bus (NA Active) An 80376 self-test may be requested at the time RE- SET goes inactive by having the BUSY input at a LOW level as shown in Figure 419 The self-test requires (220 a approximately 60) CLK2 periods to complete The self-test duration is not affected by the test results Even if the self-test indicates a problem the 80376 attempts to proceed with the reset sequence afterwards After the RESET falling edge (and after the self-test if it was requested) the 80376 performs an internal initialization sequence for approximately 350 to 450 CLK2 periods 56 |
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