376 datasheet(26/95 Pages) INTEL

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376 EMBEDDED PROCESSOR

Table 31 Access Rights Byte Definition for Code and Data Descriptors

Bit

Name

Function

Position

Present (P)

P e 1

Segment is mapped into physical memory

P e 0

No mapping to physical memory exits

6 – 5

Descriptor Privilege

Segment privilege attribute used in privilege tests

Level (DPL)

Segment

S e 1

Code or Data (includes stacks) segment descriptor

Descriptor (S)

S e 0

System Segment Descriptor or Gate Descriptor

Executable (E)

E e 0

Descriptor type is data segment

Expansion

ED e 0 Expand up segment offsets must be s limit

Data

Direction (ED)

ED e 1 Expand down segment offsets must be l limit

Segment

Writable (W)

(S e 1

W e 0 Data segment may not be written into

E e 0)

W e 1 Data segment may be written into

Executable (E)

E e 1

Descriptor type is code segment

Conforming (C)

Code

C e 1

Code segment may only be executed when

Segment

CPL t DPL and CPL remains unchanged

Readable (R)

(S e 1

R e 0 Code segment may not be read

E e 1)

R e 1 Code segment may be read

Accessed (A)

A e 0

Segment has not been accessed

A e 1

Segment selector has been loaded into segment register

or used by selector test instructions

generated that is a truncated version of this linear

address Truncation will be to the maximum number

of address bits It is recommended to place EPROM

at the highest physical address and DRAM at the

lowest physical addresses

Code and Data Descriptors (Se1)

Figure 34 shows the general format of a code and

data descriptor and Table 31 illustrates how the bits

in the Access Right Byte are interpreted

Code and data segments have several descriptor

fields in common The accessed bit A is set when-

ever the processor accesses a descriptor The gran-

ularity bit G specifies if a segment length is 1-byte-

granular or 4-Kbyte-granular

Base address bits

31 – 24 which are normally found in 80386 descrip-

tors are not made externally available on the 80376

They do not affect the operation of the 80376 The

A31–A24 field should be set to allow an 80386 to

correctly execute with EPROM at the upper 4096

Mbytes of physical memory

System Descriptor Formats (S e 0)

System segments describe information about oper-

ating system tables tasks and gates Figure 35

shows the general format of system segment de-

scriptors and the various types of system segments

80376 system descriptors (which are the same as

80386 descriptor types 2 5 9 B C E and F) contain

a 32-bit logical base address and a 20-bit segment

limit

Selector Fields

A selector has three fields Local or Global Descrip-

tor Table Indicator (TI) Descriptor Entry Index (In-

dex) and Requestor ( the selector’s) Privilege Level

(RPL) as shown in Figure 36 The TI bit selects ei-

ther the Global Descriptor Table or the Local De-

scriptor Table The Index selects one of 8K descrip-

tors in the appropriate descriptor table The RPL bits

allow high speed testing of the selector’s privilege

attributes

Segment Descriptor Cache

In addition to the selector value every segment reg-

ister has a segment descriptor cache register asso-

ciated with it Whenever a segment register’s con-

tents are changed the 8-byte descriptor associated

with that selector is automatically loaded (cached)

on the chip Once loaded all references to that seg-

ment use the cached descriptor information instead

of reaccessing the descriptor The contents of the

descriptor cache are not visible to the programmer

Since descriptor caches only change when a seg-

ment register is changed programs which modify

the descriptor tables must reload the appropriate

segment registers after changing a descriptor’s

value

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