376 datasheet(72/95 Pages) INTEL

72 / 95 page

376 EMBEDDED PROCESSOR

than the calculated clock count due to instruction

sequences which execute faster than they can be

fetched from memory

Instruction Clock Count Assumptions

1 The instruction has been prefetched decoded

and is ready for execution

2 Bus cycles do not require wait states

3 There are no local bus HOLD requests delaying

processor acess to the bus

4 No exceptions are detected during instruction ex-

ecution

5 If an effective address is calculated it does not

use two general register components One regis-

ter scaling and displacement can be used within

the clock counts showns However if the effec-

tive address calculation uses two general register

components add 1 clock to the clock count

shown

6 Memory reference instruction accesses byte or

aligned 16-bit operands

Instruction Clock Count Notation

If two clock counts are given the smaller refers to

a register operand and the larger refers to a

memory operand

n e number of times repeated

m e number of components in the next instruc-

tion executed where the entire displacement (if

any) counts as one component the entire im-

mediate data (if any) counts as one component

and all other bytes of the instruction and pre-

fix(es) each count as one component

Misaligned or 32-Bit Operand Accesses

If instructions accesses a misaligned 16-bit oper-

and or 32-bit operand on even address add

clocks for read or write

clocks for read and write

If instructions accesses a 32-bit operand on odd

address add

clocks for read or write

clocks for read and write

Wait States

Wait states add 1 clock per wait state to instruction

execution for each data access

376 Datasheet(PDF) 72 Page - Intel Corporation

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