376 datasheet(35/95 Pages) INTEL

35 / 95 page

376 EMBEDDED PROCESSOR

BUS CYCLE DEFINITION SIGNALS

(WR DC MIO LOCK)

These three-state outputs define the type of bus cy-

cle being performed WR distinguishes between

write and read cycles DC distinguishes between

data and control cycles MIO distinguishes between

memory and IO cycles and LOCK distinguishes be-

tween locked and unlocked bus cycles All of these

signals are active LOW and will float during bus ac-

knowledge

The primary bus cycle definition signals are WR

DC and MIO since these are the signals driven

valid as ADS (Address Status output) becomes ac-

tive The LOCK signal is driven valid at the same

time the bus cycle begins which due to address

pipelining could be after ADS becomes active Ex-

act bus cycle definitions as a function of WR DC

and MIO are given in Table 42

LOCK indicates that other system bus masters are

not to gain control of the system bus while it is ac-

tive LOCK is activated on the CLK2 edge that be-

gins the first locked bus cycle (ie it is not active at

the same time as the other bus cycle definition pins)

and is deactivated when ready is returned to the end

of the last bus cycle which is to be locked The be-

ginning of a bus cycle is determined when READY is

returned in a previous bus cycle and another is

pending (ADS is active) or the clock in which ADS is

driven active if the bus was idle This means that it

follows more closely with the write data rules when it

is valid but may cause the bus to be locked longer

than desired The LOCK signal may be explicitly acti-

vated by the LOCK prefix on certain instructions

LOCK is always asserted when executing the XCHG

instruction during descriptor updates and during the

interrupt acknowledge sequence

BUS CONTROL SIGNALS

(ADS READY NA)

The following signals allow the processor to indicate

when a bus cycle has begun and allow other system

hardware to control address pipelining and bus cycle

termination

Address Status (ADS)

This three-state output indicates that a valid bus cy-

cle definition and address (WR DC MIO BHE

BLE and A23–A1) are being driven at the 80376

pins ADS is an active LOW output Once ADS is

driven active valid address byte enables and defi-

nition signals will not change In addition ADS will

remain active until its associated bus cycle begins

(when READY is returned for the previous bus cycle

when running pipelined bus cycles) ADS will float

during bus hold acknowledge See sections Non-

Pipelined Bus Cycles

and Pipelined Bus Cycles

for additional information on how ADS is asserted

for different bus states

Transfer Acknowledge (READY)

This input indicates the current bus cycle is com-

plete and the active bytes indicated by BHE and

BLE are accepted or provided When READY is

sampled active during a read cycle or interrupt ac-

knowledge cycle the 80376 latches the input data

and terminates the cycle When READY is sampled

active during a write cycle the processor terminates

the bus cycle

Table 42 Bus Cycle Definition

MIO

Bus Cycle Type

Locked

INTERRUPT ACKNOWLEDGE

Yes

Does Not Occur

IO DATA READ

IO DATA WRITE

MEMORY CODE READ

HALT

SHUTDOWN

Address e 2

Address e 0

BHE e 1

BLE e 0

MEMORY DATA READ

Some Cycles

MEMORY DATA WRITE

Some Cycles

376 Datasheet(PDF) 35 Page - Intel Corporation

376 Datasheet(HTML) 35 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL