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376 Datasheet(PDF) 49 Page - Intel Corporation |
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376 Datasheet(HTML) 49 Page - Intel Corporation |
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49 / 95 page  376 EMBEDDED PROCESSOR 240182 – 27 Bus States T1first clock of a non-pipelined bus cycle (80376 drives new address status and asserts ADS) T2subsequent clocks of a bus cycle when NA has not been sampled asserted in the current bus cycle T2Isubsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle but there is not yet an internal bus request pending (80376 will not drive new address status or assert ADS) T2Psubsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle and there is an internal bus request pending (80376 drives new address status and asserts ADS) T1Pfirst clock of a pipelined bus cycle Tiidle state Thhold acknowledge state (80376 asserts HLDA) Asserting NA for pipelined bus cycles gives access to three more bus states T2I T2P and T1P Using pipelining the fastest bus cycle consists of T1P and T2P Figure 412 80376 Processor Complete Bus States (Including Pipelining) 49 |
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