PS081 datasheet(137/155 Pages) AMSCO

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6-34

PSØ81

6.5

System Reset, Sleep Mode and Auto-configuration

ALU activity is requested by a reset (power-on, watchdog), the end of measurement or in sleep mode

the end of the conversion counter. A reset has priority over the last two items. First the ALU jumps

into the ROM code starting with address 2048. There a first check is done whether the ALU was

activated after a reset or not.

In case of a reset the flag epr_pwr_cfg is checked to decide whether the auto-configuration data from

the EEPROM have to be copied into the RAM or not.

In the following flag epr_pwr_prg is checked to decide whether EEPROM code (starting at address

48) shall be executed. In stand alone operation this is reasonable and epr_pwr_cfg bit should be 1. In

front end operation this is unlikely and with epr_pwr_cfg = 0 the µP is stopped.

In case the ALU is started not by a reset the TDC unit starts a measurement or, in sleep mode, the

conversion counter is started without a measurement. Afterwards the flag epr_usr_prg is checked to

decide about a jump into the EEPROM (address 48). Again, in stand-alone operation epr_usr_prg =1

is reasonable, in front-end operation epr_usr_prg = 0 will be more likely.

In the EEPROM code first the flag flg_rstpwr should be checked to see whether the reason for the

jump was a reset. If yes, a detailed check is recommended to see whether the reset comes from a

power-on reset, a pushed button, the watchdog interrupt.

Otherwise a check of flag flg_intav0 will indicate if the chip is still in sleep mode or if an active strain

measurement is running.

At the end the ALU is stopped. This implements a complete reset of the ALU including the start

flags. Also the program stack is reset. Only the RAM data remain unchanged.

6.5.1

Power On Reset

When applying the supply voltage to the chip a power-on reset is generated. The whole chip is reset,

only the RAM remains unchanged.

In case epr_pwr_prg = 1 the user code at EEPROM address 48 is started.

6.5.2

Watchdog Reset

A power-on reset can also be triggered by the watchdog timer. This happens in case the micropro-

cessor is started four times without being reset by the opcode “clrwdt”. Status bit flg_wdtalt in regis-

ter 22, bit 17, indicates a timeout of the watchdog timer.

In case epr_pwr_prg = 1 the user code at EEPROM address 48 is started.

6.5.3

External Reset on Pin 27

In stand-alone mode (SPI_ENA = 0) it is possible to apply an external power-on at pin 27 (SPI_CSN_

RST). This can be used for a reset button. The status of the button can be requested from status bit

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