LAN9354 datasheet(22/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 22

 2015 Microchip Technology Inc.

LED 4

LED4

VO12/

VOD12/

VOS12

This pin is configured to operate as an LED when

the LED 4 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is set. The buffer type depends on

the setting of the LED Function 2-0 (LED_FUN[2:0])

field in the LED Configuration Register (LED_CFG)

and is configured to be either a push-pull or open-

drain/open-source output. When selected as an

open-drain/open-source output, the polarity of this

pin depends upon the 1588EN strap value sampled

at reset.

Note:

Refer to Section 17.3, "LED Operation,"

on page 452 to additional information.

General

Purpose I/O 4

GPIO4

VIS/VO12/

VOD12

(PU)

This pin is configured to operate as a GPIO when

the LED 4 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is clear. The pin is fully program-

mable as either a push-pull output, an open-drain

output or a Schmitt-triggered input by writing the

General Purpose I/O Configuration Register (GPI-

O_CFG) and the General Purpose I/O Data & Direc-

tion Register (GPIO_DATA_DIR).

1588 Enable

Configuration

Strap

1588EN

VIS

(PU)

This strap configures the default value of the 1588

Enable soft-strap. See Note 9.

LED 3

LED3

VO12/

VOD12/

VOS12

This pin is configured to operate as an LED when

the LED 3 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is set. The buffer type depends on

the setting of the LED Function 2-0 (LED_FUN[2:0])

field in the LED Configuration Register (LED_CFG)

and is configured to be either a push-pull or open-

drain/open-source output. When selected as an

open-drain/open-source output, the polarity of this

pin depends upon the EEEEN strap value sampled

at reset.

Note:

Refer to Section 17.3, "LED Operation,"

on page 452 to additional information.

General

Purpose I/O 3

GPIO3

VIS/VO12/

VOD12

(PU)

This pin is configured to operate as a GPIO when

the LED 3 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is clear. The pin is fully program-

mable as either a push-pull output, an open-drain

output or a Schmitt-triggered input by writing the

General Purpose I/O Configuration Register (GPI-

O_CFG) and the General Purpose I/O Data & Direc-

tion Register (GPIO_DATA_DIR).

Energy Efficient

Ethernet Enable

Configuration

Strap

EEEEN

VIS

(PU)

This strap configures the default value of the EEE

Enable 2-1 soft-straps. See Note 9.

TABLE 3-8:

GPIO, LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

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