LAN9354 datasheet(71/487 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001926B-page 71

LAN9354

For additional details on the General Purpose Timer, refer to Section 16.1, "General Purpose Timer," on page 447.

8.2.7

SOFTWARE INTERRUPT

A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt

Enable Register (INT_EN). The Software Interrupt (SW_INT) bit of the Interrupt Status Register (INT_STS) is generated

when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) changes from cleared

to set (i.e. on the rising edge of the enable). This interrupt provides an easy way for software to generate an interrupt

and is designed for general software usage.

In order for a Software interrupt event to trigger the external IRQ interrupt pin, the IRQ output must be enabled via the

IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

8.2.8

DEVICE READY INTERRUPT

A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register

(INT_EN). The Device Ready (READY) bit of the Interrupt Status Register (INT_STS) indicates that the device is ready

to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt Status Register (INT_STS) will

clear it.

In order for a device ready interrupt event to trigger the external IRQ interrupt pin, the Device Ready Enable

(READY_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the

IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

8.2.9

CLOCK OUTPUT TEST MODE

In order to facilitate system level debug, the crystal clock can be enabled onto the IRQ pin by setting the IRQ Clock

Select (IRQ_CLK_SELECT) bit of the Interrupt Configuration Register (IRQ_CFG).

The IRQ pin should be set to a push-pull driver by using the IRQ Buffer Type (IRQ_TYPE) bit for the best result.

8.3

Interrupt Registers

This section details the directly addressable interrupt related System CSRs. These registers control, configure and mon-

itor the IRQ interrupt output pin and the various device interrupt sources. For an overview of the entire directly address-

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