LAN9354 datasheet(68/487 Pages) MICROCHIP

68 / 487 page

LAN9354

DS00001926B-page 68

 2015 Microchip Technology Inc.

(IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin de-

asserts, regardless of the reason.

FIGURE 8-1:

FUNCTIONAL INTERRUPT HIERARCHY

INT_CFG

INT_STS

INT_EN

Top Level Interrupt Registers

(System CSRs)

Bit 29 (1588_EVNT)

of INT_STS register

PHY_INTERRUPT_SOURCE_B

PHY_INTERRUPT_MASK_B

PHY B Interrupt Registers

Bit 27 (PHY_INT_B)

of INT_STS register

PHY_INTERRUPT_SOURCE_A

PHY_INTERRUPT_MASK_A

PHY A Interrupt Registers

Bit 26 (PHY_INT_A)

of INT_STS register

SW_IMR

SW_IPR

Switch Fabric Interrupt Registers

Bit 28 (SWITCH_INT)

of INT_STS register

BM_IMR

BM_IPR

Buffer Manager Interrupt Registers

Bit 6 (BM)

of SW_IPR register

SWE_IMR

SWE_IPR

Switch Engine Interrupt Registers

Bit 5 (SWE)

of SW_IPR register

MAC_IMR_[2,1,0]

MAC_IPR_[2,1,0]

Port [2,1,0] MAC Interrupt Registers

Bits [2,1,0] (MAC_[2,1,0])

of SW_IPR register

PMT_CTRL

Power Management Control Register

Bit 17 (PME_INT)

of INT_STS register

GPIO_INT_STS_EN

GPIO Interrupt Register

Bit 12 (GPIO)

of INT_STS register

1588_INT_STS

1588_INT_EN

1588 Time Stamp Interrupt Registers

LAN9354 Datasheet(PDF) 68 Page - Microchip Technology

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