LAN9354 datasheet(61/487 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001926B-page 61

LAN9354

EEE_enable_strap_2

Switch Port 2 Energy Efficient Ethernet Enable Strap:

Configures the default value of the Energy Efficient Ethernet

(EEE_ENABLE) bit in the (x=2) Port x MAC Transmit Configu-

ration Register (MAC_TX_CFG_x).

Note:

This has no effect when the PHY is in 100BASE-FX

mode (lack of EEE auto-negotiation results disables

EEE).

Refer to the respective register definition sections for addi-

tional information.

EEEEN

EEE_enable_strap_2

(cont.)

PHY B Energy Efficient Ethernet Enable Strap:

This strap

affects the default value of the following register bits (x=B):

• PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit

of the PHY x EDPD NLP / Crossover Time / EEE Configu-

ration Register (PHY_EDPD_CFG_x)

• 100BASE-TX EEE bit of the PHY x EEE Capability Regis-

ter (PHY_EEE_CAP_x)

• 100BASE-TX EEE bit of the PHY x EEE Advertisement

Note:

This has no effect when the PHY is in 100BASE-FX

mode.

Refer to the respective register definition sections for addi-

tional information.

EEEEN

speed_strap_0

Note:

speed_strap_0 and

speed_pol_strap_0 share

the same strap register and

EEPROM bit.

Port 0 Virtual PHY Speed Select Strap:

This strap affects

the default value of the following bits in the (x=0) Virtual PHY

Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY):

• 100BASE-X Full Duplex

• 100BASE-X Half Duplex

• 10BASE-T Full Duplex

• 10BASE-T Half Duplex

Refer to Section 9.3.5.6 and Table 9-23 for more information.

This strap also configures the speed for Port 0 when Virtual

Auto-Negotiation fails. Refer to Section 9.2.6.2, "Parallel

Detection," on page 85 for additional information.

Refer to the respective register definition sections for addi-

tional information.

speed_pol_strap_0

Note:

speed_strap_0 and

speed_pol_strap_0 share

the same strap register and

EEPROM bit.

Switch Port 0 Speed Polarity Strap:

This strap determines

the polarity of the P0_SPEED when in Port 0 RMII MAC

mode.

0 = P0_SPEED low means 100Mbps, high means 10Mbps

1 = P0_SPEED high means 100Mbps, low means 10Mbps

Refer to the respective register definition sections for addi-

tional information.

TABLE 7-1:

SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)

Strap Name

Description

Pin / Default Value

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