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LAN9354 Datasheet(PDF) 73 Page - Microchip Technology |
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LAN9354 Datasheet(HTML) 73 Page - Microchip Technology |
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73 / 487 page  2015 Microchip Technology Inc. DS00001926B-page 73 LAN9354 Note 1: Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) is set. 4 IRQ Polarity (IRQ_POL) When cleared, this bit enables the IRQ line to function as an active low out- put. When set, the IRQ output is active high. When the IRQ is configured as an open-drain output (via the IRQ_TYPE bit), this bit is ignored and the inter- rupt is always active low. 0: IRQ active low output 1: IRQ active high output R/W NASR Note 1 0b 3:2 RESERVED RO - 1 IRQ Clock Select (IRQ_CLK_SELECT) When this bit is set, the crystal clock may be output on the IRQ pin. This is intended to be used for system debug purposes in order to observe the clock and not for any functional purpose. Note: When using this bit, the IRQ pin should be set to a push-pull driver. R/W 0b 0 IRQ Buffer Type (IRQ_TYPE) When this bit is cleared, the IRQ pin functions as an open-drain output for use in a wired-or interrupt configuration. When set, the IRQ is a push-pull driver. Note: When configured as an open-drain output, the IRQ_POL bit is ignored and the interrupt output is always active low. 0: IRQ pin open-drain output 1: IRQ pin push-pull driver R/W NASR Note 1 0b Bits Description Type Default |
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