LAN9354 datasheet(92/487 Pages) MICROCHIP

92 / 487 page

LAN9354

DS00001926B-page 92

 2015 Microchip Technology Inc.

When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be

set, and the Broadcast Frame Received (BCAST_FR) bit of the PHY x Wakeup Control and Status Register

(PHY_WUCSR_x) will be set.

9.2.12.3

Magic Packet Detection

When enabled, the Magic Packet detection mode allows the detection of a Magic Packet frame. A Magic Packet is a

frame addressed to the device - either a unicast to the programmed address, or a broadcast - which contains the pattern

48’h FF_FF_FF_FF_FF_FF after the destination and source address field, followed by 16 repetitions of the desired MAC

address (loaded into the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address

B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x)) without any

breaks or interruptions. In case of a break in the 16 address repetitions, the logic scans for the 48’h

FF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must

be preceded by the synchronization stream. The frame must also pass the FCS check and packet length checking.

As an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence

in an Ethernet frame:

Destination Address Source Address ……………FF FF FF FF FF FF

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

…FCS

As an example, the Host system must perform the following steps to enable the device to detect a Magic Packet WoL

event:

Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_AD-

DRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register

(PHY_RX_ADDRC_x).

Set the Magic Packet Enable (MPEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) to enable

Magic Packet detection.

Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable WoL

events.

When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be

set, and the Magic Packet Received (MPR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will

be set.

9.2.12.4

Wakeup Frame Detection

When enabled, the Wakeup Frame detection mode allows the detection of a pre-programmed Wakeup Frame. Wakeup

Frame detection provides a way for system designers to detect a customized pattern within a packet via a programma-

ble wake-up frame filter. The filter has a 128-bit byte mask that indicates which bytes of the frame should be compared

by the detection logic. A CRC-16 is calculated over these bytes. The result is then compared with the filter’s respective

CRC-16 to determine if a match exists. When a wake-up pattern is received, the Remote Wakeup Frame Received

(WUFR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) is set.

If enabled, the filter can also include a comparison between the frame’s destination address and the address specified

in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register

(PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The specified address can

be a unicast or a multicast. If address matching is enabled, only the programmed unicast or multicast address will be

considered a match. Non-specific multicast addresses and the broadcast address can be separately enabled. The

address matching results are logically OR’d (i.e., specific address match result OR any multicast result OR broadcast

result).

Whether or not the filter is enabled and whether the destination address is checked is determined by configuring the

PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x). Before enabling the filter, the application program

must provide the detection logic with the sample frame and corresponding byte mask. This information is provided by

writing the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x), PHY x Wakeup Filter Configuration

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