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LAN9354 Datasheet(PDF) 57 Page - Microchip Technology

Part # LAN9354
Description  3-Port 10/100 Managed Ethernet Switch
PDF  487 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9354 Datasheet(HTML) 57 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001926B-page 57
LAN9354
BP_EN_strap_1
Switch Port 1 Backpressure Enable Strap:
Configures the
default value for the Port 1 Backpressure Enable (BP_EN_1)
bit of the Port 1 Manual Flow Control Register (MANUAL_F-
C_1).
Refer to the respective register definition sections for addi-
tional information.
1b
FD_FC_strap_1
Switch Port 1 Full-Duplex Flow Control Enable Strap:
This
strap is used to configure the default value of the following
register bits:
• Port 1 Full-Duplex Transmit Flow Control Enable (TX_F-
C_1) and Port 1 Full-Duplex Receive Flow Control Enable
(RX_FC_1) bits of the Port 1 Manual Flow Control Regis-
ter (MANUAL_FC_1)
Refer to the respective register definition sections for addi-
tional information.
1b
FD_FC_strap_1
(cont.)
PHY A Full-Duplex Flow Control Enable Strap:
This strap
affects the default value of the following register bits (x=A):
• Asymmetric Pause bit of the PHY x Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
Note:
This has no effect when the PHY is in 100BASE-FX
mode.
Refer to the respective register definition sections for addi-
tional information.
1b
manual_FC_strap_1
Switch Port 1 Manual Flow Control Enable Strap:
Config-
ures the default value of the Port 1 Full-Duplex Manual Flow
Control Select (MANUAL_FC_1) bit in the Port 1 Manual Flow
Control Register (MANUAL_FC_1).
Refer to the respective register definition sections for addi-
tional information.
0b
manual_FC_strap_1
(cont.)
PHY A Manual Flow Control Enable Strap:
This strap
affects the default value of the following register bits (x=A):
• Asymmetric Pause and Symmetric Pause bit of the PHY
x Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
Note:
This has no effect when the PHY is in 100BASE-FX
mode.
Refer to the respective register definition sections for addi-
tional information.
0b
TABLE 7-1:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
Description
Pin / Default Value



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