LAN9354 datasheet(74/487 Pages) MICROCHIP

74 / 487 page

LAN9354

DS00001926B-page 74

 2015 Microchip Technology Inc.

8.3.2

INTERRUPT STATUS REGISTER (INT_STS)

This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt

conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register

reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Inter-

rupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and

clears the interrupt.

Offset:

058h

Size:

32 bits

Bits

Description

Type

Default

Software Interrupt (SW_INT)

This interrupt is generated when the Software Interrupt Enable

(SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high.

Writing a one clears this interrupt.

R/WC

Device Ready (READY)

This interrupt indicates that the device is ready to be accessed after a

power-up or reset condition.

R/WC

1588 Interrupt Event (1588_EVNT)

This bit indicates an interrupt event from the IEEE 1588 module. This bit

should be used in conjunction with the 1588 Interrupt Status Register

(1588_INT_STS) to determine the source of the interrupt event within the

1588 module.

Switch Fabric Interrupt Event (SWITCH_INT)

This bit indicates an interrupt event from the Switch Fabric. This bit should

be used in conjunction with the Switch Global Interrupt Pending Register

(SW_IPR) to determine the source of the interrupt event within the Switch

Fabric.

Physical PHY B Interrupt Event (PHY_INT_B)

This bit indicates an interrupt event from the Physical PHY B. The source of

the interrupt can be determined by polling the PHY x Interrupt Source Flags

Physical PHY A Interrupt Event (PHY_INT_A)

This bit indicates an interrupt event from the Physical PHY A. The source of

the interrupt can be determined by polling the PHY x Interrupt Source Flags

25:23

RESERVED

21:20

RESERVED

GP Timer (GPT_INT)

This interrupt is issued when the General Purpose Timer Count Register

(GPT_CNT) wraps past zero to FFFFh.

R/WC

RESERVED

LAN9354 Datasheet(PDF) 74 Page - Microchip Technology

LAN9354 Datasheet(HTML) 74 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL