LAN9354 datasheet(48/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 48

 2015 Microchip Technology Inc.

6.3.4.1

Entering Low Power Modes

To enter any of the low power modes (D1 - D3) from normal mode (D0), follow these steps:

Write the PM_MODE and PM_WAKE fields in the Power Management Control Register (PMT_CTRL) to their

desired values

Set the wake-up detection desired per Section 6.3.1, "Wake-Up Event Detection".

Set the appropriate wake-up notification per Section 6.3.2, "Wake-Up (PME) Notification".

Ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted,

receivers disabled, packets processed / flushed, etc.)

Set the PM_SLEEP_EN bit in the Power Management Control Register (PMT_CTRL).

Note:

The EEPROM Loader Register Data burst sequence (Section 12.4.5) can be used to achieve an initial

power down state without the need of software by:

•First setting the PHYs into General Purpose Power Down by

setting the PHY_PWR_DWN bit in PHY_BASIC_CONTROL_1/2

via the PMI_DATA / PMI_ACCESS registers.

•Setting the PM_MODE and PM_SLEEP_EN bits in the Power Management Control Register (PMT_C-

TRL).

Upon entering any low power mode, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG)

and the Power Management Control Register (PMT_CTRL) is forced low.

6.3.4.2

Exiting Low Power Modes

Exiting from a low power mode can be done manually or automatically.

An automatic wake-up will occur based on the events described in Section 6.3.2, "Wake-Up (PME) Notification". Auto-

matic wake-up is enabled with the Power Management Wakeup (PM_WAKE) bit in the Power Management Control

A manual wake-up is initiated by the host when:

• an I2C cycle (Start Condition detected) is performed. Although all reads and writes are ignored until the device has

been woken, the host should direct the use a read of the Byte Order Test Register (BYTE_TEST) to wake the

device. Reads and writes to any other addresses should not be attempted until the device is awake.

Note:

Since the I2C bus may have multiple slaves, the device will be woken on a cycle to any slave. This is a sys-

tem level issue which can be solved with appropriate gating logic.

• an SMI cycle (MDC high and MDIO low) is performed. Although all reads and writes are ignored until the device

has been woken, the host should direct the use a read of the Byte Order Test Register (BYTE_TEST) to wake the

device. Reads and writes to any other addresses should not be attempted until the device is awake.

Note:

Since the SMI bus may have multiple slaves, the device will be woken on a cycle to any slave. This is a

system level issue which can be solved with appropriate gating logic.

To determine when the host interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once

the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in

the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) can be

polled to determine when the device is fully awake.

Note

If supplied by the PHYs or externally

PLL is requested to be turned off and will disable if both of the PHYs are in either Energy Detect or General Power Down

PHY clocks are off, external clocks are gated off

Note:

The PM_MODE field cannot be changed at the same time as the PM_SLEEP_EN bit is set and the

PM_SLEEP_EN bit cannot be set at the same time that the PM_MODE field is changed.

Note:

Upon entry into any of the power saving states the host interfaces are not functional.

TABLE 6-2:

POWER MANAGEMENT STATES

Clock Source

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