LAN9354 datasheet(64/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 64

 2015 Microchip Technology Inc.

P0_mode_strap[1:0]

Switch Port 0 Mode Strap:

Configures the mode of opera-

tion for Port 0.

00 = (reserved)

01 = (reserved)

10 = RMII MAC Mode

11 = RMII PHY Mode

For the LAN9354 these operating modes result from the fol-

lowing mapping:

Note:

Only RMII is supported.

See Table 7-3 for the combined Port 0 mode strapping.

P0_MODE2

P0_rmii_clock_dir_strap

Switch Port 0 RMII Clock Direction Strap:

Configures the

default value of the RMII Clock Direction bit in the (x=0) Vir-

tual PHY Special Control/Status Register (VPHY_SPE-

CIAL_CONTROL_STATUS).

0 = Input

1 = Output

See Table 7-3 for the combined Port 0 mode strapping.

P0_MODE1

P0_clock_strength_strap

Switch Port 0 Clock Strength Strap: Configures the default

value of the RMII Clock Strength bit in the (x=0) Virtual PHY

Special Control/Status Register (VPHY_SPECIAL_CON-

TROL_STATUS)

0 = 12ma

1 = 16ma

See Table 7-3 for the combined Port 0 mode strapping.

P0_MODE0

TABLE 7-2:

HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)

Strap Name

Description

Pins

P0_MODE[2]

P0_mode_strap[1:0]

10 (RMII MAC)

11 (RMII PHY)

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