LAN9354 datasheet(19/487 Pages) MICROCHIP

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DS00001926B-page 19

LAN9354

Port 0 RMII

Reference Clock

P0_REFCLK

VIS/

VO12/

VO16

(PD)

Note 6

RMII MAC Mode:

This pin is an input or an output

running at 50 MHz and is used as the reference

clock for the P0_IND[1:0], P0_INDV, P0_OUTD[1:0],

and P0_OUTDV pins. The choice of input verses

output is based on the setting of the RMII Clock

Direction bit in the Port 0 Virtual PHY Special Con-

trol/Status Register (VPHY_SPECIAL_CON-

TROL_STATUS). A low selects P0_OUTCLK as an

input and a high selects P0_OUTCLK as an output.

As an input, the pull-down is enabled by default.

As an output, the input buffer and pull-down are dis-

abled. The choice of drive strength is based on the

MII Virtual PHY RMII Clock Strength bit. A low

selects a 12 mA drive, while a high selects a 16 mA

drive.

VIS/

VO12/

VO16

(PD)

Note 6

RMII PHY Mode:

This pin is an input or an output

running at 50 MHz and is used as the reference

clock for the P0_IND[1:0], P0_INDV, P0_OUTD[1:0],

and P0_OUTDV pins. The choice of input verses

output is based on the setting of the RMII Clock

Direction bit in the Port 0 Virtual PHY Special Con-

trol/Status Register (VPHY_SPECIAL_CON-

TROL_STATUS). A low selects P0_OUTCLK as an

input and a high selects P0_OUTCLK as an output.

As an input, the pull-down is normally enabled. The

input buffer and pull-down are disabled when the

Isolate (VPHY_ISO) bit is set in the Port 0 Virtual

PHY Basic Control Register (VPHY_BASIC_CTRL).

As an output, the input buffer and pull-down are dis-

abled. The choice of drive strength is based on the

MII Virtual PHY RMII Clock Strength bit. A low

selects a 12 mA drive, while a high selects a 16 mA

drive. The output driver is disabled when the Isolate

(VPHY_ISO) bit is set in the Port 0 Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL).

Port 0 Mode[0]

Configuration

Strap

P0_MODE0

VIS

(PU)

Note 8

This strap configures the mode for Port 0. See

Note 7.

Refer to Table 7-3, “Port 0 Mode Strap Mapping,” on

page 66 for the Port 0 strap settings.

TABLE 3-5:

SWITCH PORT 0 RMII & CONFIGURATION STRAP PIN DESCRIPTIONS

(CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

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