LAN9354 datasheet(95/487 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001926B-page 95

LAN9354

9.2.13

RESETS

In addition to the chip-level hardware reset (RST#) and Power-On Reset (POR), the PHY supports three block specific

resets. These are discussed in the following sections. For detailed information on all device resets and the reset

sequence refer to Section 6.2, "Resets," on page 38.

9.2.13.1

PHY Software Reset via RESET_CTL

The PHYs can be reset via the Reset Control Register (RESET_CTL). These bits are self clearing after approximately

102 us. This reset does not reload the configuration strap values into the PHY registers.

9.2.13.2

PHY Software Reset via PHY_BASIC_CTRL_x

The PHY can also be reset by setting the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BA-

SIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the

configuration strap values into the PHY registers.

9.2.13.3

PHY Power-Down Reset

After the PHY has returned from a power-down state, a reset of the PHY is automatically generated. The PHY power-

down modes do not reload or reset the PHY registers. Refer to Section 9.2.10, "PHY Power-Down Modes," on page 90

for additional information.

9.2.14

LINK INTEGRITY TEST

The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The

link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the PHY x Basic Status Register

(PHY_BASIC_STATUS_x) and to drive the LINK LED functions.

The DSP indicates a valid MLT-3 waveform present on the RXPx and RXNx signals as defined by the ANSI X3.263 TP-

PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is

asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When

received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-

ation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.

To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted

until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately

negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic.

9.2.15

CABLE DIAGNOSTICS

The PHYs provide cable diagnostics which allow for open/short and length detection of the Ethernet cable. The cable

diagnostics consist of two primary modes of operation:

• Time Domain Reflectometry (TDR) Cable Diagnostics

TDR cable diagnostics enable the detection of open or shorted cabling on the TX or RX pair, as well as cable

length estimation to the open/short fault.

• Matched Cable Diagnostics

Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables.

Refer to the following sub-sections for details on proper operation of each cable diagnostics mode.

Note:

Only a hardware reset (RST#) or Power-On Reset (POR) will automatically reload the configuration strap

values into the PHY registers.

The Digital Reset (DIGITAL_RST) bit in the Reset Control Register (RESET_CTL) does not reset the

PHYs. The Digital Reset (DIGITAL_RST) bit will cause the EEPROM Loader to reload the configuration

strap values into the PHY registers and to reset all other PHY registers to their default values. An EEPROM

RELOAD command via the EEPROM Command Register (E2P_CMD) also has the same effect.

For all other PHY resets, PHY registers will need to be manually configured via software.

Note:

Cable diagnostics are not used for 100BASE-FX mode.

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