LAN9354 datasheet(17/487 Pages) MICROCHIP

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DS00001926B-page 17

LAN9354

TABLE 3-5:

SWITCH PORT 0 RMII & CONFIGURATION STRAP PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

Port 0 RMII

Input Data 1

P0_IND1

VIS

(PD)

RMII MAC Mode:

This pin is the receive data 1 bit

from the external PHY to the switch.

VIS

(PD)

RMII PHY Mode:

This pin is the transmit data 1 bit

from the external MAC to the switch. The pull-down

and input buffer are disabled when the Isolate

(VPHY_ISO) bit is set in the Port 0 Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL).

Port 0 RMII

Input Data 0

P0_IND0

VIS

(PD)

RMII MAC Mode:

This pin is the receive data 0 bit

from the external PHY to the switch.

VIS

(PD)

RMII PHY Mode:

This pin is the transmit data 0 bit

from the external MAC to the switch. The pull-down

and input buffer are disabled when the Isolate

(VPHY_ISO) bit is set in the Port 0 Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL).

Port 0 RMII

Input Data Valid

P0_INDV

VIS

(PD)

RMII MAC Mode:

This pin is the CRS_DV signal

from the external PHY.

VIS

(PD)

RMII PHY Mode:

This pin is the TX_EN signal from

the external MAC and indicates valid data on

P0_IND[1:0]. The pull-down and input buffer are dis-

abled when the Isolate (VPHY_ISO) bit is set in the

Port 0 Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL).

Port 0 RMII

Output Data 1

P0_OUTD1

VO8

RMII MAC Mode:

This pin is the transmit data 1 bit

from the switch to the external PHY.

VO8

RMII PHY Mode:

This pin is the receive data 1 bit

from the switch to the external MAC. The output

driver is disabled when the Isolate (VPHY_ISO) bit

is set in the Port 0 Virtual PHY Basic Control Regis-

ter (VPHY_BASIC_CTRL).

Port 0 Mode[2]

Configuration

Strap

P0_MODE2

VIS

(PU)

Note 8

This strap configures the mode for Port 0. See

Note 7.

Refer to Table 7-3, “Port 0 Mode Strap Mapping,” on

page 66 for the Port 0 strap settings.

Port 0 RMII

Output Data 0

P0_OUTD0

VO8

RMII MAC Mode:

This pin is the transmit data 0 bit

from the switch to the external PHY.

VO8

RMII PHY Mode:

This pin is the receive data 0 bit

from the switch to the external MAC. The output

driver is disabled when the Isolate (VPHY_ISO) bit

is set in the Port 0 Virtual PHY Basic Control Regis-

ter (VPHY_BASIC_CTRL).

Port 0 Mode[1]

Configuration

Strap

P0_MODE1

VIS

(PU)

Note 8

This strap configures the mode for Port 0. See

Note 7.

Refer to Table 7-3, “Port 0 Mode Strap Mapping,” on

page 66 for the Port 0 strap settings.

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