LAN9354 datasheet(40/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 40

 2015 Microchip Technology Inc.

Following valid voltage levels, a POR reset typically takes approximately 21 ms, plus any additional time (91 us per byte)

for data loaded from the EEPROM. A full 64KB EEPROM load would complete in approximately 6 seconds.

6.2.1.2

RST# Pin Reset

Driving the RST# input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this

reset input is optional, but when used, it must be driven for the period of time specified in Section 20.6.3, "Reset and

Configuration Strap Timing," on page 478. Configuration straps are latched, and EEPROM loading is performed as a

result of this reset.

A RST# pin reset typically takes approximately 760

s plus any additional time (91 us per byte) for data loaded from the

EEPROM. A full 64KB EEPROM load would complete in approximately 6 seconds.

Please refer to Table 3-9, “Miscellaneous Pin Descriptions,” on page 24 for a description of the RST# pin.

6.2.2

BLOCK-LEVEL RESETS

The block level resets contain an assortment of reset register bit inputs and generate resets for the various blocks. Block

level resets can affect one or multiple modules.

6.2.2.1

Multi-Module Resets

Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration straps are not latched

upon multi-module resets. A multi-module reset is initiated by assertion of the following:

• DIGITAL RESET (DIGITAL_RST)

Multi-module reset/configuration completion can be determined by first polling the Byte Order Test Register

(BYTE_TEST). The returned data will be invalid until the Host interface resets are complete. Once the returned data is

the correct byte ordering value, the Host interface resets have completed.

The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configura-

tion Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit

indicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_C-

TRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal

resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY

bit is set.

DIGITAL RESET (DIGITAL_RST)

A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital reset

will reset all device sub-modules except the Ethernet PHYs. EEPROM loading is performed following this reset. Con-

figuration straps are not latched as a result of a digital reset. However, soft straps are first returned to their previously

latched pin values and register bits that default to strap values are reloaded.

A digital reset typically takes approximately 760

s plus any additional time (91 uS per byte) for data loaded from the

EEPROM. A full 64KB EEPROM load would complete in approximately 6 seconds.

6.2.2.2

Single-Module Resets

A single-module reset will reset only the specified module. Single-module resets do not latch the configuration straps or

initiate the EEPROM Loader. A single-module reset is initiated by assertion of the following:

• Port A PHY Reset

• Port B PHY Reset

• Virtual PHY Reset

Note:

The RST# pin is pulled-high internally. If unused, this signal can be left unconnected. Do not rely on internal

pull-up resistors to drive signals external to the device.

Note:

The digital reset does not reset register bits designated as NASR.

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