LAN9354 datasheet(91/487 Pages) MICROCHIP

91 / 487 page

 2015 Microchip Technology Inc.

DS00001926B-page 91

LAN9354

• The MAC and link-partner must support and be configured for EEE operation

• The device and link-partner must link in 100BASE-TX full-duplex mode

The value of the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit affects the default values of the following reg-

ister bits:

• 100BASE-TX EEE bit of the MMD PHY x EEE Capability Register (PHY_EEE_CAP_x)

• 100BASE-TX EEE bit of the MMD PHY x EEE Advertisement Register (PHY_EEE_ADV_x)

Note:

Energy Efficient Ethernet is not used for 100BASE-FX mode.

9.2.12

WAKE ON LAN (WOL)

The PHY supports layer WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames.

Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individually

enabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable

(MPEN), and Wakeup Frame Enable (WUEN) bits of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x),

respectively. The WoL event is indicated via the INT8 bit of the PHY x Interrupt Source Flags Register (PHY_INTER-

RUPT_SOURCE_x).

The WoL feature is part of the broader power management features of the device and can be used to trigger the power

management event or general interrupt request pin (IRQ). This is accomplished by enabling the WoL feature of the PHY

as described above, and setting the corresponding WoL enable (bit 14 for PHY A, bit 15 for PHY B) of the Power Man-

agement Control Register (PMT_CTRL). Refer to Section 6.3, "Power Management," on page 45 for additional informa-

tion.

The PHY x Wakeup Control and Status Register (PHY_WUCSR_x) also provides a WoL Configured bit, which may be

set by software after all WoL registers are configured. Because all WoL related registers are not affected by software

resets, software can poll the WoL Configured bit to ensure all WoL registers are fully configured. This allows the software

to skip reprogramming of the WoL registers after reboot due to a WoL event.

The following subsections detail each type of WoL event. For additional information on the main system interrupts, refer

to Section 8.0, "System Interrupts," on page 67.

9.2.12.1

Perfect DA (Destination Address) Detection

When enabled, the Perfect DA detection mode allows the detection of a frame with the destination address matching

the address stored in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address

B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The frame

must also pass the FCS and packet length check.

As an example, the Host system must perform the following steps to enable the device to detect a Perfect DA WoL

event:

Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX-

_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address

C Register (PHY_RX_ADDRC_x).

Set the Perfect DA Wakeup Enable (PFDA_EN) bit of the PHY x Wakeup Control and Status Register

(PHY_WUCSR_x) to enable Perfect DA detection.

Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable

WoL events.

When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be

set, and the Perfect DA Frame Received (PFDA_FR) bit of the PHY x Wakeup Control and Status Register

(PHY_WUCSR_x) will be set.

9.2.12.2

Broadcast Detection

When enabled, the Broadcast detection mode allows the detection of a frame with the destination address value of FF

FF FF FF FF FF. The frame must also pass the FCS and packet length check.

As an example, the Host system must perform the following steps to enable the device to detect a Broadcast WoL event:

Set the Broadcast Wakeup Enable (BCST_EN) bit of the PHY x Wakeup Control and Status Register

(PHY_WUCSR_x) to enable Broadcast detection.

Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable

WoL events.

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