LAN9354 datasheet(18/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 18

 2015 Microchip Technology Inc.

Port 0 RMII

Output Data

Valid

P0_OUTDV

VO8

RMII MAC Mode:

This pin is the TX_EN signal to

the external PHY.

VO8

RMII PHY Mode:

This pin is the CRS_DV signal to

the external MAC. The output driver is disabled

when the Isolate (VPHY_ISO) bit is set in the Port 0

Virtual PHY Basic Control Register (VPHY_BA-

SIC_CTRL).

Port 0 Speed

P0_SPEED

VIS

(PU)

RMII MAC Mode:

This pin can be changed at any

time (live value) and is typically tied to the speed

indication from the external PHY. It can be overrid-

den by the Speed Select LSB (VPHY_-

SPEED_SEL_LSB) bit in the Port 0 Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL) by

clearing the Auto-Negotiation (VPHY_AN) bit in the

same register.

The polarity of this pin is determined by the

speed_pol_strap_0.

RMII PHY Mode:

This pin is not used.

Port 0 RMII

Duplex

P0_DUPLEX

VIS

(PU)

RMII MAC Mode:

This pin can be changed at any

time (live value) and is typically tied to the duplex

indication from the external PHY. It can be overrid-

den by the Duplex Mode (VPHY_DUPLEX) bit in the

Port 0 Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL) by clearing the Auto-Negoti-

ation (VPHY_AN) bit in the same register.

The polarity of this pin is determined by the duplex-

_pol_strap_0.

RMII PHY Mode:

This pin is not used.

TABLE 3-5:

SWITCH PORT 0 RMII & CONFIGURATION STRAP PIN DESCRIPTIONS

(CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

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