LAN9354 datasheet(44/487 Pages) MICROCHIP

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LAN9354

DS00001926B-page 44

 2015 Microchip Technology Inc.

Port B PHY Reset (PHY_B_RST)

Setting this bit resets the Port B PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port B PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 12.4.5).

R/W

Port A PHY Reset (PHY_A_RST)

Setting this bit resets the Port A PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port A PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 12.4.5).

R/W

Digital Reset (DIGITAL_RST)

Setting this bit resets the complete chip except the PLL, Virtual PHY, Port B

PHY and Port A PHY. All system CSRs are reset except for any NASR type

bits. Any in progress EEPROM commands (including RELOAD) are termi-

nated.

The EEPROM Loader will automatically reload the configuration following

this reset, but will not reset the Virtual PHY, Port B PHY or Port A PHY. If

desired, the above PHY resets can be issued once the device is configured.

When the chip is released from reset, this bit is automatically cleared. All

writes to this bit are ignored while this bit is set.

Note:

This bit is not accessible via the EEPROM Loader’s register

initialization function (Section 12.4.5).

R/W

Bits

Description

Type

Default

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