LP3910 datasheet(34/72 Pages) TI1

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hiRef

loRef

ntc

Logic

charger

control

Battery discharge

Constant Voltage Charging

Battery charge current

Battery voltage

Time

Full Rate

Topoff

RED LED

GREEN LED

OFF

End-Of-Charge

(EOC)

50% Duty cycle

Pre-qualification

2.85V

Charging restart voltage

3.9V, 4.0V or 4.2V

Termination voltage

4.1V, 4.2V or 4.38V

1.0C

0.1 C PREQUAL CURRENT

0.05 C EOC CURRENT

LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

www.ti.com

Figure 55. Charge Cycle Complete

8.3.4.5 Battery Temperature Monitoring (TS Pin)

The LP3910 is equipped with a battery thermistor terminal to continuously monitor the battery temperature by

measuring the voltage between the TS pin and GND. With the TS pin connected to the battery thermistor,

charging is allowed only if the battery temperature is within the acceptable temperature range set by a pair of

internal comparators inside the LP3910. The temperature window is 0°C to 45°C or 0°C to 50°C, depending on

the setting of D2 of the charger supervisory (CHSPV) register. There is 3°C of temperature hysteresis associated

with each temperature threshold. The default temperature range is 0°C to 50°C and can be changed to 0°C to

45°C by setting bit D3 in the CHSPV register. If the battery temperature is out of range, STAT2, STAT1, and

STAT0 bits in the CHSPV register are set to logic1, logic0, logic0, and charging is suspended.

The TS pin is only active during charging and draws no current from the battery when no external power source

is present.

If the TS pin is not used in the application, it must be connected to GND through a 100-k

Ω pulldown resistor.

When the TS pin is left floating (battery removal), the charger is disabled as the TS voltage exceeds the lower

temperature limit.

Figure 56. Battery Temperature Monitor with TS Pin

8.3.4.6 Disabling Charger

Charging can be safely interrupted by clearing the Charge enable bit D1 in the Charge Control Register and can

subsequently resume upon setting this bit. When the charger is disabled, STAT2, STAT1, and STAT0 bits in the

CHSPV register are set to logic 0.

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