LP3910 datasheet(47/72 Pages) TI1

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LP3910

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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

8.4.2.3 Power-Off Timing

The timing delays during a power-off sequence are equal to 63 ms minus the timing delay during the power on

sequence (see Table 10).

Table 10. Power-Off Timing Defaults

TIME (STANDARD

SYMBOL

DESCRIPTION

TIME (AP option)

UNIT

OPTIONS)

Delay for LDO1 and LDO2

Delay to Buck1

Delay for Buck2

Delay for Buck-Boost

Delay for NRST

8.4.2.4 Transitioning From Standby to Active Mode (Power Up) Battery Power Present Only

When only battery power is present and the battery voltage VBATT > VBATTLOW, the LP3910 is waiting for one of

three valid wakeup signals. The first is the ONOFF pin. The second and third wakeups are the wall adapter and

USBPWR. The ONOFF pin is a factory-programmable wakeup source. It can be a rising edge, a falling edge, a

level high, or a level low event. Regardless of the mode, the signal requires a 32-ms deglitch time. A deglitched

version of the ONOFF pin is output on the open-drain output pin ONSTAT. ONOFF is usually connected to a

push button. Asserting the ONOFF pin starts the power-on sequencer. This enables the DC-DC converters,

including the Buck1 DC-DC converter that supplies power to the system processor. The system processor then

must set bit D4 (PACK bit) in the power-on event register through the I2C interface or apply a logic high to the

POWERACK pin to keep the device in the Active mode. These serve as power acknowledgment, confirming the

power-on request initiated by the ONOFF pin. If neither the PACK bit (D4) in the PON register or the

POWERACK pin is set within 128 ms (maximum) of the start of the power-up sequencer, the LP3910 is

automatically turned off, as the system has failed to acknowledge the power-on request. Connecting the battery

is considered a power-on event. However, hot insertion of the battery with the adapter connected is NOT

permitted.

8.4.2.5 Transitioning From Active Mode to Standby Mode

8.4.2.5.1

External Event Triggers the Transition From Active to Standby Mode

When the device is active, a subsequent re-assertion of the push button turns off the LP3910 indirectly by first

flagging the system processor though the ONSTAT pin. Upon detecting the ONSTAT transition, the system

processor must clear bit D4 (PACK) in the power on event register and apply a logic low to the POWERACK pin

to power down the LP3910, which then transitions to Standby Mode. Clearing the PACK register bit and

POWERACK pin while external supply sources are present (either USB or CHG_IN) does not power down the

LP3910, to keep the charger active. The system can as always disable all necessary DC-DC converters, except

Buck1, through the register control.

When external power is disconnected, LP3910 remains in its active state unless the battery voltage is below VBLA

(battery low alarm) or unless the PACK (either bit D4 in the PON register and the POWERACK pin) is cleared by

the system processor.

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