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LP3910 Datasheet(PDF) 37 Page - Texas Instruments |
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LP3910 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 72 page  To ADC core Icharge Scaler Vbatt Scaler MUX_CONTROL VBATT 2 ISET ADC1 ADC2 ADC MUX Current range 0 / 1 Voltage range 0 / 1 LP3910 www.ti.com SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015 Figure 59. ADC Analog Front-End Block Diagram The source selection and the access to the conversion results are established through the I2C linked control registers: ADCC and ADCD. The ADC is by default disabled to minimize current consumption and must be enabled by setting D2 in the ADCC register. Writing a logic 1 to bit D3 in the ADC initiates a conversion. It is advised to select the correct ADC source before a conversion is started. The ADC sets bit D4 in the ADCC register upon the completion of a conversion, which is typically 4 ms after the start of the conversion. At the same time an interrupt request is generated. (See IRQ Register (0d)H Interrupt Request Register). To save power, disable the ADC by setting bit 2 of D2 to 0. To make repetitive starts, set bit D3 to 0 then to 1 for register 0Ah to initiate start of conversion. The interrupt driven protocol between LP3910 and the system processor is the most efficient way to acquire data from successive measurements as shown in Figure 60: Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links: LP3910 |
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