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LP3910 Datasheet(PDF) 6 Page - Texas Instruments |
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LP3910 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 72 page  LP3910 SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015 www.ti.com Pin Functions (continued) PIN I/O TYPE(1) DESCRIPTION NO. NAME 21 VIN2 I PWR Power input to Buck1. VIN2 pin must be externally shorted to the VDD pins. 22 VIN3 I PWR Power input to Buck2. VIN3 pin must be externally shorted to the VDD pins. 23 VBUCK2 O A Buck2 Output 24 BCKGND2 — G Buck2 Ground 25 VFB2 I A Buck2 Feedback input terminal Power ONOFF pin configured either as level (High or Low) triggered or edge (High or 26 ONOFF I D Low) triggered. 27 I2C_SCL I D I2C-compatible interface clock terminal 28 VDDIO I D Supply to input / output stages of digital I/O 29 I2C_SDA I/O D I2C-compatible interface data terminal Open 30 ONSTAT O Open Drain output that reflects the debounced state of ONOFF pin. Drain 31 VBBFB I A Buck-Boost Feedback input terminal 32 VBBOUT O A Buck-Boost Output voltage 33 VBBL2 I A Buck-Boost inductor 34 BBGND1 — G Buck-Boost high current ground 35 VBBL1 I A Buck-Boost inductor 36 VIN4 I PWR Power input to Buck-Boost. VIN4 pin must be externally shorted to the VDD pins. 37 USBSUSP I D This pin must be pulled high during USB suspend mode. Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits 38 USBISEL I D the USB charge current to 500 mA. 39 BBGND2 — G BUCK-BOOST Core Ground 40 DGND — G Digital ground Power input to supply application. This pin must be externally shorted to VDD1 and 41 VDD3 I PWR VDD2. Power input to supply application This pin must be externally shorted to VDD1 and 42 VDD2 I PWR VDD3. 43 VBATT3 O A Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2. 44 VBATT2 O A Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3. 45 USBPWR I PWR USB power input pin 46 VDD1 I PWR Power input to supply application This pin is shorted to VDD2 and VDD3. 47 CHG_DET I A Wall adapter power input pin A 121-k Ω resistor must be connected between this pin and AGND. The resistor value 48 IREF I A determines the reference current for the internal bias generator. 6 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LP3910 |
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