LP3910 datasheet(35/72 Pages) TI1

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Control

Logic

Integrator

Comparator

8 Bit ADC

Dready

Overflow

Data

Enable

START

1&2

1&3

Vsignal

Vbias

LP3910

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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

8.3.4.7 Safety Timer

In order to prevent endless charging, which could degrade the battery quality and life time, the LP3910 contains

a safety timer that limits charging regardless whether the battery has reached its full capacity or not. In

prequalification the safety timer is 1 hour. In full rate or constant voltage charging the safety timer is a maximum

of 10 hours minus the time in prequalification.

When the timer times out of uninterrupted charging, an IRQ is generated to alert system processor. The status of

the timer can also be polled by reading the IRQ register if the system doesn’t support hardware interrupts.

The safety timer resets and starts counting from zero upon the following events:

1. Power ON (through connecting valid power to either USBPWR or CHGN_IN pins).

2. Interchanging USBPWR and CHG_IN sources.

3. The voltage of a charged battery drops below the restart value, and the charger is enabled.

4. Disabling and re-enabling of the charger by toggling bit D1 of the Charge Control Register.

5. Emerging from thermal shutdown.

6. Emerging from a battery temperature out-of-range, and the charger is enabled.

7. Emerging from USB suspend mode when charging with USB power.

8.3.4.8 Charging Maintenance

When a fully charged battery is being loaded by the system while the external power is present and while bit D1

in the charge control register is set to a 1 (charge enable) then the charging restarts when the battery voltage

drops below the charging restart threshold. The value of the threshold depends on the termination voltage

according to the following table:

Table 6. Charging Thresholds

VTERM

CHARGING RESTART VOLTAGE

4.1 V

3.9 V

4.2 V

4 V

4.38 V

4.2 V

8.3.5 ADC

The LP3910 is equipped with an 8-bit dual-slope integrating an ADC. Dual-slope converters provide effective

filtering of > 500-kHz and < 125-kHz noise components on the input voltage, and does not require a sample and

hold stage. The ADC core digitizes the input voltage ranging from VREF to 2VREF, where VREF is the voltage

measured on the VREFH pin. After an initial 2-ms warm-up for the first activation of the ADC enable bit, the dual-

slope converter integrates the input signal during the first phase for approximately 2 ms, followed by a second

phase that integrates VREF for 0 ms to 2 ms depending on the level of the input signal. As a result the total

conversion time varies from 2 ms to 4 ms.

Figure 57. Simplified ADC Block Diagram

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LP3910 Datasheet(PDF) 35 Page - Texas Instruments

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