LP3910 datasheet(10/72 Pages) TI1

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LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

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7.8 Detection and Timing

Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IPROG = 500 mA

10% EOC setting

IEOC

End-of-charge current

IPROG = 500 mA

5% EOC setting

VTERM = 4.1 V

3.82

3.9

3.94

Battery restart charging

VRESTART

VTERM = 4.2 V

3.94

4.06

voltage

VTERM = 4.38 V

4.14

4.2

4.26

7.9 Output Electrical Characteristics: CHG, STAT

Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical limits apply for TJ = 25°C;

minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.

(1) (2) (3) (4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VLED = 2 V

CHSPV Register (02)h bit 5 = 1

(standard)

ILED

Output high level

VLED = 2 V

CHSPV Register (02)h bit 5 = 1 (AP

0.75

1.25

version only)

VLED = 2 V

CHSPV Register (02)h bit 5 = 0

(standard)

ILED

Output high level

VLED = 2 V

CHSPV Register (02)h bit 5 = 0 (AP

1.6

2.4

version only)

ILEAKAGE

Leakage current

VLED = 1.5 V, LED off

0.1

µA

LEDFREQ

Blinking frequency

0.8

1.2

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(3)

Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the

most likely norm.

(4)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

7.10 Output Electrical Characteristics: NRST, IRQB, ONSTAT

Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply over

the entire junction temperature range for operation, TJ = 0°C to 125°C.

(1) (2) (3) (4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOL

Output low level

IOL = 4 mA

0.4

ILEAKAGE

Leakage current

VDD = 2.5 V, output logic high

–1

µA

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(3)

Minimum and maximum limits are specified by design, test, or statistical analysis.

(4)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

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