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LP3910 Datasheet(PDF) 51 Page - Texas Instruments

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Part # LP3910
Description  Power Management IC for Hard-Drive-Based Portable Media Players
PDF  72 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LP3910 Datasheet(HTML) 51 Page - Texas Instruments

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ack from slave
w ack
start
msb Chip Address lsb
msb Register Add lsb
msb
DATA
lsb
ack
ack stop
ack from slave
ack from slave
SCL
start
id = K¶60
w ack
register addr = K¶10
GDWD DGGU K¶6A
ack
ack stop
SDA
rs
msb Chip Address lsb
r
ack
repeated start
data from slave
ack from master
r
id = K¶60
ack
rs
SCL
SDA
start
id = K¶60
w ack
addr = K¶00
DGGUHVV K¶$$ GDWD
ack
ack
stop
ack from slave
w ack
start
msb Chip Address lsb
msb Register Add lsb
msb
DATA
lsb
ack
ack
stop
ack from slave
ack from slave
1
2
3
4
5 6
7
8
9
1
2
3 ...
ADR6
bit7
MSB
R/W
LSB
1
1
0
0
0
0
0
ADR5
bit6
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR1
bit1
ADR4
bit5
bit0
I
2
C SLAVE address (chip address)
LP3910
www.ti.com
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
Programming (continued)
Figure 71. I2C Chip Address
w = write (I2C_SDA = 0)
r = read (I2C_SDA = 1)
ack = acknowledge (I2C_SDA pulled down by either master or slave)
rs = repeated start
id = LP3910 chip address: 60’h
Figure 72. I2C Write Cycle
8.5.1.6 Register Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown
Figure 73.
Figure 73. I2C Read Cycle
8.5.1.7 Multi-Byte I2C Command Sequence
The I2C serial interface of the LP3910 device supports random register multi-byte command sequencing: during
a multi-byte write the Master sends the Start command followed by the device address, which is sent only once,
followed by the 8-bit register address, then 8 bits of data, The I2C slave must then accept the next random
register address followed by 8 bits of data and continue this process until the master sends a valid stop
condition.
Copyright © 2006–2015, Texas Instruments Incorporated
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Product Folder Links: LP3910



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