LP3910 datasheet(48/72 Pages) TI1

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ONSTAT

NRST

ONOFF

POWERACK

VREFH

Power Down Caused by External Event

64 ms

5 ms

t4 t3

32 ms

deglitch

(Bit D4 in PON register and

POWERBACK pin)

BUCK/BOOST

VBUCK2

VBUCK1

VLDO1, VLDO2

(To Microprocessor)

(From Microprocessor)

LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

www.ti.com

Figure 67. Power-Down Event Caused by External Event

8.4.2.5.2

Transition From Active to Standby Mode Due to Expiring POWERACK Deadline

With no external charger present when the system processor fails to acknowledge the power-on in time by

setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following

the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources

are disabled before transitioning to Standby Mode. This 2-ms delay allows the microprocessor to receive a clean

reset before the power is de-asserted. A new power-on event is then required to transition back to active mode.

With either external charger present when the system processor fails to acknowledge the power-on in time by

setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following

the start of the power-up sequencer, the NRST is immediately de-asserted; after 2 ms all power sources are

disabled before transitioning to charger standby mode.

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