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LP3910 Datasheet(PDF) 52 Page - Texas Instruments |
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LP3910 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 72 page  ack from slave ack from slave ack from slave w ack start msb Chip Address lsb msb Register Add lsb msb DATA lsb ack ack stop msb Register Add lsb ack msb DATA lsb ack ack from slave ack from slave Register 0x2A Register 0x24 LP3910 SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015 www.ti.com Programming (continued) A typical multi-byte random register transfer is: Device Address, Register A Address, Ack, Register A Data, Ack Register M Address, Ack, Register M Data, Ack Register X Address, Ack, Register X Data, Ack Register Z Address, Ack, Register Z Data, Ack, Stop NOTE The PMIC is not required to detect the I2C device address for each transaction. A, M, X, and Z are random numbers. Figure 74. Example Multi-Byte Command Sequencing 52 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LP3910 |
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