LP3910 datasheet(46/72 Pages) TI1

46 / 72 page

Clock

Divider

Oscillator

Comparator

6 Bit Up /

Down

Counter

1 kHz

LDO1, LDO2

Buck1

Buck2

Buck - Boost

NRST

down

LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

www.ti.com

8.4.2 Mode Sequencing

8.4.2.1 Power-On, Power-Off Sequencing

Each DC-DC converter (Buck1, Buck2, Buck-Boost, LDO1, LDO2) and the NRST pin of the LP3910 has its own

delay after which it is enabled following a power-on event or disabled following a power-off event. Following the

deglitching of the power-on event, the system bandgaps are enabled. Following this is a 5 ms delay that internal

circuitry requires to cleanly power up. The programmable delays are measured from this time point. Following the

deglitching of a power-down event (up to 5 ms if POWERACK pin is used), the power-down sequencer starts.

Each delay ranges from 0 ms to 63 ms in steps of 1 ms and is factory programmed to the desired values

submitted by the system designer. As shown in Figure 66, the power-on or power-off sequencing is designed

around a 6-bit up or down timer that is clocked at 1 kHz. A power-on or power-off event triggers the timer, which

counts up from 0 during a power-on sequence and counts down from 5'b11111 during a power-down cycle. The

timer output is connected to 5 comparators with factory-programmed timeout values that correspond to the on

and off delays for each DC-DC converter and the NRST pin. Once the timer has incremented beyond the

comparator timeout value during a power-on cycle, the output of the comparator enables the corresponding DC-

DC converter or raises the NRST pin to a logic high level. Subsequently, once the timer has decremented below

the comparator timeout value during a power-down cycle, the output of the comparator disables the

corresponding DC-DC converter or activates the NRST pin to a logic low level.

Figure 66. Power Sequencer Block Diagram

8.4.2.2 Power-On Timing

Each timeout T1 thru to T5 are factory programmed from 0 ms to 63 ms. The power-on defaults are shown in

Table 9.

Table 9. Power-On Timing Defaults

TIME (STANDARD

SYMBOL

DESCRIPTION

TIME (AP OPTION)

UNIT

OPTIONS)

Delay for LDO1 and LDO2

Delay to Buck1

Delay for Buck2

Delay for Buck-Boost

Delay for NRST

Submit Documentation Feedback

Product Folder Links: LP3910

LP3910 Datasheet(PDF) 46 Page - Texas Instruments

LP3910 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL