LP3910 datasheet(14/72 Pages) TI1

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LP3910

SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

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7.18 Electrical Characteristics: ADC

All limits apply for TJ = 25°C unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TJ = 25°C

1.22

1.225

1.23

VREF

Reference voltage

TJ = 0°C to 125°C

1.2

1.225

1.23

INL

Core ADC integral non-linearity

VREF = 1.225

(1)

–1

LSB

DNL

Core ADC differential non-linearity VREF = 1.225

(1)

–0.5

0.5

LSB

General purpose ADC input

VGP_IN

VREF

2 × VREF

voltage range

Battery maximum voltage scalar

VBATT = 3.5 V

2.435

2.45

2.465

output

VBATT,

RANGE 0

Battery minimum voltage scalar

VBATT = 2.6 V

1.217

1.225

1.232

output

Battery maximum voltage scalar

VBATT = 4.4 V

2.435

2.45

2.465

output

VBATT,

RANGE 1

Battery minimum voltage scalar

VREF = 2.6 V

1.217

1.225

1.232

output

VISENSE = 0.6463 V

ISENSE maximum voltage scalar

ICHG = 0.605 A,

2.373

2.45

2.519

output

RSENSE = 4.64 kΩ

VISENSE ,

RANGE 0

VISENSE = 0 V

ISENSE minimum voltage scalar

ICHG = 0 A,

1.186

1.225

1.260

output

RSENSE = 4.64 kΩ

VISENSE = 1.175 V

ISENSE maximum voltage scalar

ICHG = 1.1 A,

2.373

2.45

2.519

output

RSENSE = 4.64 kΩ

VISENSE,

RANGE 1

VISENSE = 0 V

ISENSE minimum voltage scalar

ICHG = 0 A,

1.186

1.225

1.26

output

RSENSE = 4.64 kΩ

ADC1 and

ADC1 and ADC2 minimum

VREFH = 1.225 V

1.218

1.225

1.23

ADC2MIN

voltage scalar output

ADC1 and

ADC1 and ADC2 maximum

VREFH = 1.225 V

2.436

2.45

2.46

ADC2MAX

voltage scalar output

tCONV

Conversion time(1)

tWARM

Warm-up time

(1)

This specification is ensured by design.

7.19 I

2C Timing Requirements

Unless otherwise noted, VDDIO = 3.6 V and minimum and maximum limits apply for TJ = 0°C to 125°C.

(1)

MIN

NOM

MAX

UNIT

FCLK

Clock frequency

400

kHz

tBF

Bus-free time between START and STOP

1.3

µs

tHOLD

Hold time repeated START condition

0.6

µs

tCLK-LP

CLK low period

1.3

µs

tCLK-HP

CLK high period

0.6

µs

tSU

Set-up time repeated START condition

0.6

µs

tDATA-HOLD

Data hold time

µs

tDATA-SU

Data set-up time

100

tSU

Set-up time for STOP condition

0.6

µs

Maximum pulse width of spikes that must be suppressed by the input filter

tTRANS

of both data and CLK signals

µs

TJ = 25°C

(1)

These specifications are ensured by design.

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