ADSP-SC583 datasheet(101/168 Pages) AD

101 / 168 page

Preliminary Technical Data

Rev. PrF

Page 101 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

DDR3 SDRAM Clock and Control Cycle Timing

Table 53 and Figure 23 show mobile DDR3 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC).

Table 53. DDR3 SDRAM Clock and Control Cycle Timing VDD_DMCx Nominal 1.5 V1

1 Specifications apply to both DMC0 and DMC1.

All specifications are based on simulation data and are subject to change without notice.

450 MHz2

2 In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD).

Parameter

Min

Max

Unit

Timing Requirements

tCK

Clock Cycle Time (CL = 2 Not Supported)

2.22

tCH

Minimum Clock Pulse Width

0.47

0.53

tCK

tCL

Maximum Clock Pulse Width

0.47

0.53

tCK

tIS

Control/Address Setup Relative to DMCx_CK Rise

0.2

tIH

Control/Address Hold Relative to DMCx_CK Rise

0.275

Figure 23. DDR3 SDRAM Clock and Control Cycle Timing

NOTE: CONTROL =

DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.

ADDRESS = DMCx_A0-A15, AND DMCx_BA0-BA2.

DMCx_CK

DMCx_Ax

DMCx CONTROL

tIS

tIH

tCK

tCH

tCL

DMCx_CK

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