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ADSP-SC583 Datasheet(PDF) 104 Page - Analog Devices |
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ADSP-SC583 Datasheet(HTML) 104 Page - Analog Devices |
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104 / 168 page  Rev. PrF | Page 104 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Enhanced Parallel Peripheral Interface Timing The following tables and figures describe enhanced parallel peripheral interface (EPPI) timing operations. The POLC bits in the EPPI_CTL register may be used to set the sampling/driving edges of the EPPI clock. When internally generated, the programmed PPI clock (fPCLKPROG) frequency in MHz is set by the following equation where VALUE is a field in the EPPI_CLKDIV register that can be set from 0 to 65535: When externally generated the EPPI_CLK is called fPCLKEXT: Table 56. Enhanced Parallel Peripheral Interface—Internal Clock All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSFSPI External FS Setup Before EPPI_CLK 6.5 ns tHFSPI External FS Hold After EPPI_CLK 0 ns tSDRPI Receive Data Setup Before EPPI_CLK 6.5 ns tHDRPI Receive Data Hold After EPPI_CLK 0 ns tSFS3GI External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock Gating Mode 14 ns tHFS3GI External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock Gating Mode 0ns Switching Characteristics tPCLKW EPPI_CLK Width1 1 See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tPCLKPROG. 0.5 × tPCLKPROG – 1.5 ns tPCLK EPPI_CLK Period1 tPCLKPROG – 1.5 ns tDFSPI Internal FS Delay After EPPI_CLK 3.5 ns tHOFSPI Internal FS Hold After EPPI_CLK –0.5 ns tDDTPI Transmit Data Delay After EPPI_CLK 3.5 ns tHDTPI Transmit Data Hold After EPPI_CLK –0.5 ns fPCLKPROG f SCLK0 VALUE 1 + ---------------------------- = tPCLKPROG 1 fPCLKPROG ----------------- = tPCLKEXT 1 fPCLKEXT -------------- = |
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