ADSP-SC583 datasheet(102/168 Pages) AD

102 / 168 page

Rev. PrF

Page 102 of 168

February 2016

Preliminary Technical Data

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

DDR3 SDRAM Read Cycle Timing

Table 54 and Figure 24 show mobile DDR3 SDRAM read cycle timing, related to the dynamic memory controller (DMC).

Table 54. DDR3 SDRAM Read Cycle Timing VDD_DMCx Nominal 1.5 V1

1 Specifications apply to both DMC0 and DMC1.

All specifications are based on simulation data and are subject to change without notice.

450 MHz2

2 In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD).

Parameter

Min

Max

Unit

Timing Requirements

tDQSQ

DMCx_DQS-DMCx_DQ Skew for DMCx_DQS and Associated DMCx_DQ

Signals

0.2

tQH

DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS

0.38

tCK

tRPRE

Read Preamble

0.9

tCK

tRPST

Read Postamble

0.3

tCK

Figure 24. DDR3 SDRAM Controller Input AC Timing

DMCx_CKx

DMCx_LDQS/DMCx_UDQS

tRPRE

tDQSQ

tQH

tRPST

DMCx_DQx

DMCx_CKx

DMCx_LDQS/DMCx_UDQS

tCK

tCH

tCL

tQH

DMCx_Ax

DMCx CONTROL

NOTE: CONTROL =

DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.

ADDRESS = DMCx_A00-13, AND DMCx_BA0-1.

ADSP-SC583 Datasheet(PDF) 102 Page - Analog Devices

ADSP-SC583 Datasheet(HTML) 102 Page - Analog Devices

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