ADSP-SC583 datasheet(103/168 Pages) AD

103 / 168 page

Preliminary Technical Data

Rev. PrF

Page 103 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

DDR3 SDRAM Write Cycle Timing

Table 55 and Figure 25 show mobile DDR3 SDRAM output ac timing, related to the dynamic memory controller (DMC).

Table 55. DDR3 SDRAM Write Cycle Timing VDD_DMCx Nominal 1.5 V1

1 Specifications apply to both DMC0 and DMC1.

All specifications are based on simulation data and are subject to change without notice.

450 MHz2

2 In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD).

Parameter

Min

Max

Unit

Switching Characteristics

tDQSS

DMCx_DQS Latching Rising Transitions to Associated Clock Edges3

3 Write command to first DMCx_DQS delay = WL × tCK + tDQSS.

–0.25

0.25

tCK

tDS

Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns)

0.125

tDH

DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns)

0.150

tDSS

DMCx_DQS Falling Edge to Clock Setup Time

0.2

tCK

tDSH

DMCx_DQS Falling Edge Hold Time From DMCx_CK

0.2

tCK

tDQSH

DMCx_DQS Input High Pulse Width

0.45

0.55

tCK

tDQSL

DMCx_DQS Input Low Pulse Width

0.45

0.55

tCK

tWPRE

Write Preamble

0.9

tCK

tWPST

Write Postamble

0.3

tCK

tIPW

Address and Control Output Pulse Width

0.840

tDIPW

DMCx_DQ and DMCx_DM Output Pulse Width

0.550

Figure 25. DDR3 SDRAM Controller Output AC Timing

tDS

tDH

tDQSS

tDSH

tDSS

tWPRE

tDQSL

tDQSH

tWPST

DMCx_CK

tIPW

tDIPW

DMCx_LDQS/DMCx_UDQS

DMCx_CK

DMCx_Ax

DMCx CONTROL

DMC0_DQSn

DMCx_LDM

DMCx_DQx

DMCx_UDM

NOTE: CONTROL =

DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.

ADDRESS = DMCx_A00-13, AND DMCx_BA0-1.

ADSP-SC583 Datasheet(PDF) 103 Page - Analog Devices

ADSP-SC583 Datasheet(HTML) 103 Page - Analog Devices

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