ELANSC520 datasheet(7/440 Pages) AMD

7 / 440 page

Table of Contents

Élan™SC520 Microcontroller Register Set Manual

vii

CHAPTER 10

GENERAL-PURPOSE BUS CONTROLLER REGISTERS

10-1

10.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

GP Echo Mode (GPECHO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

GP Chip Select Data Width (GPCSDW). . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

GP Chip Select Qualification (GPCSQUAL) . . . . . . . . . . . . . . . . . . . . . . . 10-5

GP Chip Select Recovery Time (GPCSRT) . . . . . . . . . . . . . . . . . . . . . . . 10-7

GP Chip Select Pulse Width (GPCSPW) . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

GP Chip Select Offset (GPCSOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

GP Read Pulse Width (GPRDW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

GP Read Offset (GPRDOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

GP Write Pulse Width (GPWRW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

GP Write Offset (GPWROFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

GPALE Pulse Width (GPALEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

GPALE Offset (GPALEOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

CHAPTER 11

GP DMA CONTROLLER REGISTERS

11-1

11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

GP-DMA Control (GPDMACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

GP-DMA Memory-Mapped I/O (GPDMAMMIO). . . . . . . . . . . . . . . . . . . . 11-5

GP-DMA Resource Channel Map A (GPDMAEXTCHMAPA) . . . . . . . . . 11-6

GP-DMA Resource Channel Map B (GPDMAEXTCHMAPB) . . . . . . . . . 11-8

GP-DMA Channel 0 Extended Page (GPDMAEXTPG0) . . . . . . . . . . . . 11-10

GP-DMA Channel 1 Extended Page (GPDMAEXTPG1) . . . . . . . . . . . . 11-11

GP-DMA Channel 2 Extended Page (GPDMAEXTPG2) . . . . . . . . . . . . 11-12

GP-DMA Channel 3 Extended Page (GPDMAEXTPG3) . . . . . . . . . . . . 11-13

GP-DMA Channel 5 Extended Page (GPDMAEXTPG5) . . . . . . . . . . . . 11-14

GP-DMA Channel 6 Extended Page (GPDMAEXTPG6) . . . . . . . . . . . . 11-15

GP-DMA Channel 7 Extended Page (GPDMAEXTPG7) . . . . . . . . . . . . 11-16

GP-DMA Channel 3 Extended Transfer Count (GPDMAEXTTC3). . . . . 11-17

GP-DMA Channel 5 Extended Transfer Count (GPDMAEXTTC5). . . . . 11-18

GP-DMA Channel 6 Extended Transfer Count (GPDMAEXTTC6). . . . . 11-19

GP-DMA Channel 7 Extended Transfer Count (GPDMAEXTTC7). . . . . 11-20

Buffer Chaining Control (GPDMABCCTL) . . . . . . . . . . . . . . . . . . . . . . . 11-21

Buffer Chaining Status (GPDMABCSTA) . . . . . . . . . . . . . . . . . . . . . . . . 11-22

Buffer Chaining Interrupt Enable (GPDMABSINTENB) . . . . . . . . . . . . . 11-24

Buffer Chaining Valid (GPDMABCVAL) . . . . . . . . . . . . . . . . . . . . . . . . . 11-25

GP-DMA Channel 3 Next Address Low (GPDMANXTADDL3). . . . . . . . 11-26

GP-DMA Channel 3 Next Address High (GPDMANXTADDH3) . . . . . . . 11-27

GP-DMA Channel 5 Next Address Low (GPDMANXTADDL5). . . . . . . . 11-28

GP-DMA Channel 5 Next Address High (GPDMANXTADDH5) . . . . . . . 11-29

GP-DMA Channel 6 Next Address Low (GPDMANXTADDL6). . . . . . . . 11-30

GP-DMA Channel 6 Next Address High (GPDMANXTADDH6) . . . . . . . 11-31

GP-DMA Channel 7 Next Address Low (GPDMANXTADDL7). . . . . . . . 11-32

GP-DMA Channel 7 Next Address High (GPDMANXTADDH7) . . . . . . . 11-33

GP-DMA Channel 3 Next Transfer Count Low (GPDMANXTTCL3) . . . . 11-34

GP-DMA Channel 3 Next Transfer Count High (GPDMANXTTCH3) . . . 11-35

GP-DMA Channel 5 Next Transfer Count Low (GPDMANXTTCL5) . . . . 11-36

GP-DMA Channel 5 Next Transfer Count High (GPDMANXTTCH5) . . . 11-37

GP-DMA Channel 6 Next Transfer Count Low (GPDMANXTTCL6) . . . . 11-38

GP-DMA Channel 6 Next Transfer Count High (GPDMANXTTCH6) . . . 11-39

GP-DMA Channel 7 Next Transfer Count Low (GPDMANXTTCL7) . . . . 11-40

GP-DMA Channel 7 Next Transfer Count High (GPDMANXTTCH7) . . . 11-41

Slave DMA Channel 0 Memory Address (GPDMA0MAR) . . . . . . . . . . . 11-42

Slave DMA Channel 0 Transfer Count (GPDMA0TC) . . . . . . . . . . . . . . 11-43

Slave DMA Channel 1 Memory Address (GPDMA1MAR) . . . . . . . . . . . 11-44

Slave DMA Channel 1 Transfer Count (GPDMA1TC) . . . . . . . . . . . . . . 11-45

Slave DMA Channel 2 Memory Address (GPDMA2MAR) . . . . . . . . . . . 11-46

Slave DMA Channel 2 Transfer Count (GPDMA2TC) . . . . . . . . . . . . . . 11-47

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