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ELANSC520 Datasheet(PDF) 167 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 167 Page - Advanced Micro Devices

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GP DMA Controller Registers
Élan™SC520 Microcontroller Register Set Manual
11-35
GP-DMA Channel 3 Next Transfer Count High (GPDMANXTTCH3)
Memory-Mapped
MMCR Offset DB2h
Register Description
This register provides bits 23–16 of the next transfer count for Channel 3 in buffer chaining mode.
Bit Definitions
Programming Notes
The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL
register (see page 11-21).
In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers.
Very large transfers could cause the PCI Host Bridge target controller to violate the 10-µs memory write maximum
completion time limit set in the
PCI Local Bus Specification, Revision 2.2.
7
6
5
4
3
2
1
0
Bit
DMA3_NXT_TC[23
–16]
Reset
00000000
R/W
R/W
Bit
Name
Function
7–0
DMA3_NXT_
TC[23
–16]
DMA Channel 3 Next Transfer Count High
This bit field provides bits 23–16 of the next transfer count to be used by Channel 3 in the
buffer chaining mode.



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