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FS5502 Datasheet(PDF) 15 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Bit Symbol Description Report an error in the Communication (I2C) COM_ERR = I2C_M_CRC or I2C_M_REQ or FS_COM_G 0 No failure 1 Failure 23 COM_ERR Reset condition: Real time information - cleared when all individual bits are cleared Report a wake-up event by WAKE1 or WAKE2 WU_G = WK1FLG or WK2FLG 0 No wake event 1 Wake event 22 WU_G Reset condition: Real time information - cleared when all individual bits are cleared Report an event on VPRE (status change or failure) VPRE_G = VPREOC or VPREUVH or VPREUVL or VPRE_FB_OV 0 No event 1 Event occurred 21 VPRE_G Reset condition: Real time information - cleared when all individual bits are cleared Report an event on BUCK1 (status change or failure) VBUCK1_G = BUCK1OC or BUCK1OT 0 No event 1 Event occurred 19 VBUCK1_G Reset condition: Real time information - cleared when all individual bits are cleared Report an event on BUCK3 (status change or failure) VBUCK3_G = BUCK3OC or BUCK3OT 0 No event 1 Event occurred 17 VBUCK3_G Reset condition: Real time information - cleared when all individual bits are cleared Report an event on LDO1 (status change or failure) VLDO1_G = LDO1OC or LDO1OT 0 No event 1 Event occurred 16 VLDO1_G Reset condition: Real time information Main domain I2C communication CRC issue 0 No error 1 Error detected in the I2C CRC 9 I2C_M_CRC Reset condition: POR / clear on write (write 1) Invalid main domain I2C access (wrong Write or Read, Write to INIT registers in normal mode, wrong address) 0 No error 1 I2C violation 8 I2C_M_REQ Reset condition: POR / clear on Write (write 1) Table 8. M_FLAG register bit description FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 15 / 113 |
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