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FS5502 Datasheet(PDF) 50 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 50 Page - NXP Semiconductors |
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50 / 113 page ![]() NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Address Register Bit Symbol Value Description VMON1 undervoltage threshold configuration 0000 95.5 % 0001 95 % 0010 94.5 % 0011 94 % 0100 93.5 % 0101 93 % 0110 92.5 % 0111 92 % 1000 91.5 % 1001 91 % 1010 90.5 % 1011 90 % 1100 89.5 % 1101 89 % 1110 88.5 % 10 OTP_CFG_UVOV_7 3 to 0 VMON1UVTH[3:0] 1111 88 % RSTB assignment to PGOOD 0 Not assigned 6 PGOOD_RSTB 1 Assigned VMON1 assignment to PGOOD 0 Not assigned 2 PGOOD_VMON1 1 Assigned VDDIO assignment to PGOOD 0 Not assigned 1 PGOOD_VDDIO 1 Assigned VCORE (BUCK1) assignment to PGOOD 0 Not assigned 12 OTP_CFG_PGOOD 0 PGOOD_VCORE 1 Assigned VMON1 monitoring enable 0 Disabled 14 OTP_CFG_ASIL 0 VMON1_EN 1 Enabled Device I2C address 0000 Address D0 … … 15 OTP_CFG_I2C 3 to 0 FS_I2CDEVADDR[3:0] 1111 Address D15 Table 60. Fail-safe OTP bit description...continued FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 50 / 113 |
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