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FS5502 Datasheet(PDF) 40 Page - NXP Semiconductors

Part # FS5502
Description  High voltage PMIC with multiple SMPS and LDO
PDF  113 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS5502 Datasheet(HTML) 40 Page - NXP Semiconductors

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NXP Semiconductors
FS5502
High voltage PMIC with multiple SMPS and LDO
12 OTP bits configuration
12.1 Overview
Legend:
bold — Regulator behavior in case of TSD and VPRE slew rate parameters can be changed later by I2C.
Name
Address
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
OTP_CFG_VPRE_1
14
0
0
VPREV[5:0]
OTP_CFG_VPRE_2
15
0
0
VPRESC[5:0]
OTP_CFG_VPRE_3
16
VPREILIM[1:0]
1
0
1
1
VPRESRHS[1:0]
OTP_CFG_BOOST_1
17
0
0
0
0
0000
OTP_CFG_BOOST_2
18
0
00
00000
OTP_CFG_BOOST_3
19
0
0
0
0
0
1
00
OTP_CFG_BUCK1_1
1A
VB1V[7:0]
OTP_CFG_BUCK1_2
1B
0
0
0
VB1INDOPT[1:0]
VB1SWILIM[1:0]
0
OTP_CFG_BUCK1_3
1C
00000000
OTP_CFG_BUCK1_4
1D
0
00
0
00
0
0
OTP_CFG_BUCK3_1
1E
BUCK3EN
VB3INDOPT[1:0]
VB3V[4:0]
OTP_CFG_BUCK3_2
1F
000
VB1GMCOMP[2:0]
VB3SWILIM[1:0]
OTP_CFG_LDO
20
0
000
LDO1ILIM
LDO1V[2:0]
OTP_CFG_SEQ_1
21
0
0
111
VB1S[2:0]
OTP_CFG_SEQ_2
22
0
0
111
LDO1S[2:0]
OTP_CFG_SEQ_3
23
DVS_BUCK1[1:0]
DVS_BUCK3[1:0]
Tslot
VB3S[2:0]
OTP_CFG_CLOCK_1
24
0
0
VPRE_ph[2:0]
1
0
0
OTP_CFG_CLOCK_2
25
0
0
BUCK1_ph[2:0]
000
OTP_CFG_CLOCK_3
26
0
0
BUCK3_ph[2:0]
000
OTP_CFG_CLOCK_4
27
BUCK3_
clk_sel
0
BUCK1_
clk_sel
0
VPRE_clk_sel
PLL_sel
0
1
OTP_CFG_SM_1
28
0
0
conf_TSD[5:0]
OTP_CFG_SM_2
29
0
0
0
VPRE_off_dly
1
1
PSYNC_CFG
PSYNC_EN
OTP_CFG_VSUP_UV
2A
0
0
0
0
0
0
0
VSUPCFG
OTP_CFG_I2C
2B
0
0
0
0
M_I2CDEVADDR[3:0]
OTP_CFG_OV
2C
0
0
0
0
0
VDDIO_REG_ASSIGN[2:0]
OTP_CFG_DEVID
2D
DeviceID[7:0]
Table 57. Main OTP_REGISTERS
FS5502
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 27 October 2021
40 / 113



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