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FS5502 Datasheet(PDF) 75 Page - NXP Semiconductors |
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FS5502 Datasheet(HTML) 75 Page - NXP Semiconductors |
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75 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Clock synchronization (FOUT) VFOUT_OUT Output voltage range — VDDIO — V FOUTVOL FOUT low voltage threshold at 2.0 mA — — 0.5 V FOUTVOH FOUT high voltage threshold at −2.0 mA VDDIO − 0.5 — — V IFOUT Tri-state leakage current (VDDIO = 5.0 V) −1.0 — 1.0 μA FOUTTRISE FOUT rise time (from 20 % to 80 % of VDDIO, Cout = 30 pF) — — 20 ns FOUTTFALL FOUT fall time (from 80 % to 20 % of VDDIO, Cout = 30 pF) — — 20 ns PLLTLOCK PLL lock time — — 90 μs PLLTSET PLL settling time (from EXT_FIN_DIS enable to ±1 % of output frequency) — — 125 μs Table 69. Electrical characteristics...continued 19 I/O interface pins 19.1 WAKE1, WAKE2 WAKE pins are used to manage the internal biasing of the device and the main state machine transitions. • When WAKE1 or WAKE2 is > WAKE12VIH, the internal biasing is started and the equivalent digital state is 1 • When WAKE1 or WAKE2 is < WAKE12VIL, the equivalent digital state is 0 • When WAKE1 and WAKE2 are < WAKE12AVIL, the internal biasing is stopped if the device was in Standby mode WAKE1 can be, for example, connected to VBAT and WAKE2 to the wake-up output of a CAN or FlexRay transceiver. When a WAKE pin is used as a global pin, a CRC protection is required (see Section 26 "Application information"). TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit WAKE12AVIL Analog low input voltage threshold 1 — — V WAKE12VIL Digital low input voltage threshold 2 — — V WAKE12VIH Digital high input voltage threshold — — 4 V Input current leakage at WAKE12 = 36 V — — 100 µA IWAKE12 Input current leakage at WAKE12 = 60 V — — 300 μA TWAKE12 Filtering time 50 70 100 μs Table 70. WAKE1, WAKE2 electrical characteristics 19.2 INTB INTB is an open drain output pin with internal pull up to VDDIO. This pin generates a pulse when an internal interrupt occurs to inform the MCU. Each interrupt can be masked by setting the corresponding inhibit interrupt bit in M_INT_MASK registers. TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit INTBPULL-up Internal pull-up resistor to VDDIO 5.5 10 15 kΩ Table 71. INTB electrical characteristics FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 75 / 113 |
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