FS5502 datasheet(9/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

from VPRE ON to NORMAL_M is not completed within 1 second, the device goes back

to Standby mode. VPRE restarts when VSUP > VSUP_UVH and WAKE1 or WAKE2 >

WAKE12VIH.

The device goes to Standby mode by an I2C command from the MCU. The device goes

to Standby mode when both WAKE1 and WAKE 2 = 0. The device goes to Standby

mode following the power down sequence to stop all the regulators in the reverse order

of the power up sequence. VPRE shutdown can be delayed from 250 μs to 32 ms by

OTP_VPRE_off_dly bit in case VPRE is supplying an external PMIC to wait its power

down sequence completion.

In case of loss of VPRE (VPRE < VPRE_UVL) or loss of VBOS (VBOS < VBOS_UVL), the

device stops and goes directly to Standby mode without power down sequence. VPRE

restarts when VSUP > VSUP_UVH and WAKE1 or WAKE2 > WAKE12VIH.

In case of VPRE_FB_OV detection, or TSD detection on a regulator depending on

OTP_conf_tsd[5:0] bits configuration, or deep fail-safe request from the fail-safe state

machine when DFS = 1, the device stops and goes directly to DEEP-FS mode without

power down sequence.

Exit of DEEP-FS mode is only possible by WAKE1 = 0 or after 4 s if the autoretry feature

is activated by OTP_Autorety_en bit. The number of autoretry can be limited to 15 or

infinite depending on OTP_Autoretry_infinite bit. VPRE restarts when VSUP > VSUP_UVH

and WAKE1 or WAKE2 > WAKE12VIH.

8.3 Fail-safe state machine

The fail-safe state machine starts when VBOS > VBOS_POR. RSTB and PGOOD pins are

released and the initialization of the device is opened.

When RSTB and PGOOD pins are released, the device is ready for application running

mode with all the selected monitoring activated. From now on, the FS5502 reacts

by asserting the pins (PGOOD, RSTB) according to its configuration when a fault is

detected.

8.4 Power sequencing

VPRE is the first regulator to start automatically, before the SLOT_0. The other regulators

are starting from the OTP power sequencing configuration. Seven slots are available

to program the start-up sequence of BUCK1, BUCK 3 and LDO1 regulators. The delay

between each slot is configurable to 250 µs or 1 ms by OTP using OTP_Tslot bit to

accommodate the different ramp up speed of BUCK1 and BUCK3.

The power up sequence starts at SLOT_0 and ends at SLOT_7 while the power down

sequence is executed in reverse order. All the SLOTs are executed even if there is no

regulator assigned to a SLOT. The regulators assigned to SLOT_7 are not started during

the power up sequence. They can be started (or not) later in Normal_M mode with an I2C

command to write in M_REG_CTRL1 register, if they are enabled by OTP.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

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